blob: 65ebaaa2bdaae809a66d9bdf0ced3fa44d85a860 [file] [log] [blame]
Michal Simek2a47faa2023-04-14 08:43:51 +02001# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
Michal Simek91794362022-08-31 16:45:14 +02002# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
Jay Buddhabhatti26e138a2022-12-21 23:03:35 -08003# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Michal Simek91794362022-08-31 16:45:14 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6
7PLAT_PATH := plat/xilinx/versal_net
8
Akshay Belsarecbb0c232022-10-11 15:12:02 +05309# A78 Erratum for SoC
10ERRATA_A78_AE_1941500 := 1
11ERRATA_A78_AE_1951502 := 1
12ERRATA_A78_AE_2376748 := 1
13ERRATA_A78_AE_2395408 := 1
14
Michal Simek91794362022-08-31 16:45:14 +020015override PROGRAMMABLE_RESET_ADDRESS := 1
16PSCI_EXTENDED_STATE_ID := 1
17SEPARATE_CODE_AND_RODATA := 1
18override RESET_TO_BL31 := 1
19PL011_GENERIC_UART := 1
Prasad Kummari4837d742023-05-15 11:03:37 +053020IPI_CRC_CHECK := 0
Michal Simek91794362022-08-31 16:45:14 +020021GIC_ENABLE_V4_EXTN := 0
22GICV3_SUPPORT_GIC600 := 1
Jay Buddhabhattic6daff02022-09-05 02:56:32 -070023TFA_NO_PM := 0
Michal Simek91794362022-08-31 16:45:14 +020024
25override CTX_INCLUDE_AARCH32_REGS := 0
26
Jay Buddhabhattic6daff02022-09-05 02:56:32 -070027ifdef TFA_NO_PM
28 $(eval $(call add_define,TFA_NO_PM))
29endif
30
Michal Simek91794362022-08-31 16:45:14 +020031ifdef VERSAL_NET_ATF_MEM_BASE
32 $(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE))
33
34 ifndef VERSAL_NET_ATF_MEM_SIZE
35 $(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE")
36 endif
37 $(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE))
38
39 ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE
40 $(eval $(call add_define,VERSAL_NET_ATF_MEM_PROGBITS_SIZE))
41 endif
42endif
43
44ifdef VERSAL_NET_BL32_MEM_BASE
45 $(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE))
46
47 ifndef VERSAL_NET_BL32_MEM_SIZE
48 $(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE")
49 endif
50 $(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE))
51endif
52
Prasad Kummari4837d742023-05-15 11:03:37 +053053ifdef IPI_CRC_CHECK
54 $(eval $(call add_define,IPI_CRC_CHECK))
55endif
56
Michal Simek91794362022-08-31 16:45:14 +020057USE_COHERENT_MEM := 0
58HW_ASSISTED_COHERENCY := 1
59
60VERSAL_NET_CONSOLE ?= pl011
Akshay Belsare50a29682023-01-18 15:54:12 +053061ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1 dcc))
Akshay Belsare0babc5f2023-01-13 14:40:37 +053062else
63 $(error Please define VERSAL_NET_CONSOLE)
64endif
65
Michal Simek91794362022-08-31 16:45:14 +020066$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE}))
67
Amit Nagalefefcd42023-07-10 10:43:29 +053068ifdef XILINX_OF_BOARD_DTB_ADDR
69$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
70endif
71
Amit Nagal82d0e0f2023-10-30 12:25:49 +053072# enable assert() for release/debug builds
73ENABLE_ASSERTIONS := 1
74
Michal Simek91794362022-08-31 16:45:14 +020075PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
76 -Iplat/xilinx/common/include/ \
Michal Simekaa5443e2022-09-19 14:04:55 +020077 -Iplat/xilinx/common/ipi_mailbox_service/ \
Michal Simekdc708ac2022-09-19 13:52:54 +020078 -I${PLAT_PATH}/include/ \
79 -Iplat/xilinx/versal/pm_service/
Michal Simek91794362022-08-31 16:45:14 +020080
81# Include GICv3 driver files
82include drivers/arm/gic/v3/gicv3.mk
83include lib/xlat_tables_v2/xlat_tables.mk
84include lib/libfdt/libfdt.mk
85
86PLAT_BL_COMMON_SOURCES := \
Akshay Belsare50a29682023-01-18 15:54:12 +053087 drivers/arm/dcc/dcc_console.c \
Michal Simek91794362022-08-31 16:45:14 +020088 drivers/delay_timer/delay_timer.c \
89 drivers/delay_timer/generic_delay_timer.c \
90 ${GICV3_SOURCES} \
91 drivers/arm/pl011/aarch64/pl011_console.S \
Michal Simek23551e82023-09-18 10:14:10 +020092 plat/common/aarch64/crash_console_helpers.S \
Michal Simek91794362022-08-31 16:45:14 +020093 plat/arm/common/arm_common.c \
94 plat/common/plat_gicv3.c \
95 ${PLAT_PATH}/aarch64/versal_net_helpers.S \
Akshay Belsarea103aa72023-11-08 14:27:22 +053096 ${PLAT_PATH}/aarch64/versal_net_common.c \
97 ${PLAT_PATH}/plat_topology.c \
98 ${XLAT_TABLES_LIB_SRCS}
Michal Simek91794362022-08-31 16:45:14 +020099
100BL31_SOURCES += drivers/arm/cci/cci.c \
101 lib/cpus/aarch64/cortex_a78_ae.S \
102 lib/cpus/aarch64/cortex_a78.S \
Jay Buddhabhattic6daff02022-09-05 02:56:32 -0700103 plat/common/plat_psci_common.c
104ifeq ($(TFA_NO_PM), 0)
Jay Buddhabhatti26e138a2022-12-21 23:03:35 -0800105BL31_SOURCES += plat/xilinx/common/pm_service/pm_api_sys.c \
Jay Buddhabhattic6daff02022-09-05 02:56:32 -0700106 plat/xilinx/common/pm_service/pm_ipi.c \
107 ${PLAT_PATH}/plat_psci_pm.c \
Jay Buddhabhatti26e138a2022-12-21 23:03:35 -0800108 plat/xilinx/common/pm_service/pm_svc_main.c \
Jay Buddhabhattic6daff02022-09-05 02:56:32 -0700109 ${PLAT_PATH}/pm_service/pm_client.c \
110 ${PLAT_PATH}/versal_net_ipi.c
111else
112BL31_SOURCES += ${PLAT_PATH}/plat_psci.c
113endif
Amit Nagalefefcd42023-07-10 10:43:29 +0530114BL31_SOURCES += plat/xilinx/common/plat_fdt.c \
115 plat/xilinx/common/plat_startup.c \
Prasad Kummaria8e5a582023-09-20 10:12:41 +0530116 plat/xilinx/common/plat_console.c \
Michal Simekaa5443e2022-09-19 14:04:55 +0200117 plat/xilinx/common/ipi.c \
118 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
Akshay Belsareff8e19b2023-04-03 16:18:00 +0530119 plat/xilinx/common/versal.c \
Michal Simek91794362022-08-31 16:45:14 +0200120 ${PLAT_PATH}/bl31_versal_net_setup.c \
Michal Simek91794362022-08-31 16:45:14 +0200121 common/fdt_fixup.c \
Prasad Kummaria8e5a582023-09-20 10:12:41 +0530122 common/fdt_wrappers.c \
Michal Simek91794362022-08-31 16:45:14 +0200123 ${LIBFDT_SRCS} \
124 ${PLAT_PATH}/sip_svc_setup.c \
Akshay Belsarea103aa72023-11-08 14:27:22 +0530125 ${PLAT_PATH}/versal_net_gicv3.c