Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 1 | /* |
Rohit Mathew | a0dd307 | 2024-02-03 17:22:54 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <platform_def.h> |
Chandni Cherukuri | 8271885 | 2018-08-02 12:29:07 +0530 | [diff] [blame] | 10 | #include <cortex_a75.h> |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 11 | #include <neoverse_n1.h> |
shriram.k | e69c60b | 2021-08-11 17:39:30 +0530 | [diff] [blame] | 12 | #include <neoverse_v1.h> |
shriram.k | 0fef7b6 | 2021-08-11 17:36:17 +0530 | [diff] [blame] | 13 | #include <neoverse_n2.h> |
Deepak Pandey | b561536 | 2018-10-11 13:44:43 +0530 | [diff] [blame] | 14 | #include <cpu_macros.S> |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 15 | |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 16 | .globl plat_arm_calc_core_pos |
Chandni Cherukuri | 8271885 | 2018-08-02 12:29:07 +0530 | [diff] [blame] | 17 | .globl plat_reset_handler |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 18 | |
| 19 | /* ----------------------------------------------------- |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 20 | * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) |
| 21 | * |
| 22 | * Helper function to calculate the core position. |
Vijayenthiran Subramaniam | dde6d3e | 2019-10-29 15:56:41 +0530 | [diff] [blame] | 23 | * (ChipId * PLAT_ARM_CLUSTER_COUNT * |
| 24 | * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) + |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 25 | * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) + |
| 26 | * (CPUId * CSS_SGI_MAX_PE_PER_CPU) + |
| 27 | * ThreadId |
| 28 | * |
| 29 | * which can be simplified as: |
| 30 | * |
Vijayenthiran Subramaniam | dde6d3e | 2019-10-29 15:56:41 +0530 | [diff] [blame] | 31 | * ((((ChipId * PLAT_ARM_CLUSTER_COUNT) + ClusterId) * |
| 32 | * CSS_SGI_MAX_CPUS_PER_CLUSTER) + CPUId) * CSS_SGI_MAX_PE_PER_CPU + |
| 33 | * ThreadId |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 34 | * ------------------------------------------------------ |
| 35 | */ |
| 36 | |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 37 | func plat_arm_calc_core_pos |
Vijayenthiran Subramaniam | dde6d3e | 2019-10-29 15:56:41 +0530 | [diff] [blame] | 38 | mov x4, x0 |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 39 | |
| 40 | /* |
| 41 | * The MT bit in MPIDR is always set for SGI platforms |
| 42 | * and the affinity level 0 corresponds to thread affinity level. |
| 43 | */ |
| 44 | |
| 45 | /* Extract individual affinity fields from MPIDR */ |
Vijayenthiran Subramaniam | dde6d3e | 2019-10-29 15:56:41 +0530 | [diff] [blame] | 46 | ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS |
| 47 | ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS |
| 48 | ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS |
| 49 | ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 50 | |
| 51 | /* Compute linear position */ |
Vijayenthiran Subramaniam | dde6d3e | 2019-10-29 15:56:41 +0530 | [diff] [blame] | 52 | mov x4, #PLAT_ARM_CLUSTER_COUNT |
| 53 | madd x2, x3, x4, x2 |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 54 | mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER |
| 55 | madd x1, x2, x4, x1 |
Vijayenthiran Subramaniam | dde6d3e | 2019-10-29 15:56:41 +0530 | [diff] [blame] | 56 | mov x4, #CSS_SGI_MAX_PE_PER_CPU |
| 57 | madd x0, x1, x4, x0 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 58 | ret |
| 59 | endfunc plat_arm_calc_core_pos |
Chandni Cherukuri | 8271885 | 2018-08-02 12:29:07 +0530 | [diff] [blame] | 60 | |
Chandni Cherukuri | 8271885 | 2018-08-02 12:29:07 +0530 | [diff] [blame] | 61 | /* ----------------------------------------------------- |
| 62 | * void plat_reset_handler(void); |
| 63 | * |
| 64 | * Determine the CPU MIDR and disable power down bit for |
| 65 | * that CPU. |
| 66 | * ----------------------------------------------------- |
| 67 | */ |
| 68 | func plat_reset_handler |
| 69 | jump_if_cpu_midr CORTEX_A75_MIDR, A75 |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 70 | jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 |
shriram.k | e69c60b | 2021-08-11 17:39:30 +0530 | [diff] [blame] | 71 | jump_if_cpu_midr NEOVERSE_V1_MIDR, V1 |
shriram.k | 0fef7b6 | 2021-08-11 17:36:17 +0530 | [diff] [blame] | 72 | jump_if_cpu_midr NEOVERSE_N2_MIDR, N2 |
Chandni Cherukuri | 8271885 | 2018-08-02 12:29:07 +0530 | [diff] [blame] | 73 | ret |
| 74 | |
| 75 | /* ----------------------------------------------------- |
| 76 | * Disable CPU power down bit in power control register |
| 77 | * ----------------------------------------------------- |
| 78 | */ |
| 79 | A75: |
| 80 | mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 |
| 81 | bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK |
| 82 | msr CORTEX_A75_CPUPWRCTLR_EL1, x0 |
| 83 | isb |
| 84 | ret |
Chandni Cherukuri | 044e27a | 2018-08-07 14:52:55 +0530 | [diff] [blame] | 85 | |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 86 | N1: |
| 87 | mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 |
| 88 | bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK |
| 89 | msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 |
Chandni Cherukuri | 044e27a | 2018-08-07 14:52:55 +0530 | [diff] [blame] | 90 | isb |
| 91 | ret |
shriram.k | e69c60b | 2021-08-11 17:39:30 +0530 | [diff] [blame] | 92 | |
| 93 | V1: |
| 94 | mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 |
| 95 | bic x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 96 | msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 |
| 97 | isb |
| 98 | ret |
shriram.k | 0fef7b6 | 2021-08-11 17:36:17 +0530 | [diff] [blame] | 99 | |
| 100 | N2: |
| 101 | mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 |
| 102 | bic x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT |
| 103 | msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 |
| 104 | isb |
| 105 | ret |
Chandni Cherukuri | 8271885 | 2018-08-02 12:29:07 +0530 | [diff] [blame] | 106 | endfunc plat_reset_handler |