Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | 6077dce | 2016-01-27 11:31:06 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <assert.h> |
| 9 | #include <debug.h> |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 10 | #include <delay_timer.h> |
Isla Mitchell | e363146 | 2017-07-14 10:46:32 +0100 | [diff] [blame] | 11 | #include <flowctrl.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 12 | #include <mmio.h> |
| 13 | #include <platform.h> |
| 14 | #include <platform_def.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 15 | #include <pmc.h> |
Isla Mitchell | e363146 | 2017-07-14 10:46:32 +0100 | [diff] [blame] | 16 | #include <psci.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 17 | #include <tegra_def.h> |
| 18 | #include <tegra_private.h> |
| 19 | |
Varun Wadekar | 071b787 | 2015-07-08 17:42:02 +0530 | [diff] [blame] | 20 | /* |
| 21 | * Register used to clear CPU reset signals. Each CPU has two reset |
| 22 | * signals: CPU reset (3:0) and Core reset (19:16). |
| 23 | */ |
| 24 | #define CPU_CMPLX_RESET_CLR 0x454 |
| 25 | #define CPU_CORE_RESET_MASK 0x10001 |
| 26 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 27 | /* Clock and Reset controller registers for system clock's settings */ |
| 28 | #define SCLK_RATE 0x30 |
| 29 | #define SCLK_BURST_POLICY 0x28 |
| 30 | #define SCLK_BURST_POLICY_DEFAULT 0x10000000 |
| 31 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 32 | static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
| 33 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 34 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 35 | psci_power_state_t *req_state) |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 36 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 37 | int state_id = psci_get_pstate_id(power_state); |
| 38 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 39 | /* Sanity check the requested state id */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 40 | switch (state_id) { |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 41 | case PSTATE_ID_CORE_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 42 | /* |
| 43 | * Core powerdown request only for afflvl 0 |
| 44 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 45 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; |
| 46 | |
| 47 | break; |
| 48 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 49 | case PSTATE_ID_CLUSTER_IDLE: |
| 50 | case PSTATE_ID_CLUSTER_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 51 | /* |
| 52 | * Cluster powerdown/idle request only for afflvl 1 |
| 53 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 54 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
Varun Wadekar | dba8007 | 2016-09-01 14:56:17 -0700 | [diff] [blame] | 55 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 56 | |
| 57 | break; |
| 58 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 59 | case PSTATE_ID_SOC_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 60 | /* |
| 61 | * System powerdown request only for afflvl 2 |
| 62 | */ |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 63 | for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 64 | req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
| 65 | |
| 66 | req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = |
| 67 | PLAT_SYS_SUSPEND_STATE_ID; |
| 68 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 69 | break; |
| 70 | |
| 71 | default: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 72 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
| 73 | return PSCI_E_INVALID_PARAMS; |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | return PSCI_E_SUCCESS; |
| 77 | } |
| 78 | |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 79 | /******************************************************************************* |
| 80 | * Platform handler to calculate the proper target power level at the |
| 81 | * specified affinity level |
| 82 | ******************************************************************************/ |
| 83 | plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, |
| 84 | const plat_local_state_t *states, |
| 85 | unsigned int ncpu) |
| 86 | { |
| 87 | plat_local_state_t target = *states; |
| 88 | int cpu = plat_my_core_pos(); |
| 89 | int core_pos = read_mpidr() & MPIDR_CPU_MASK; |
| 90 | |
| 91 | /* get the power state at this level */ |
| 92 | if (lvl == MPIDR_AFFLVL1) |
| 93 | target = *(states + core_pos); |
| 94 | if (lvl == MPIDR_AFFLVL2) |
| 95 | target = *(states + cpu); |
| 96 | |
| 97 | /* Cluster idle/power-down */ |
| 98 | if ((lvl == MPIDR_AFFLVL1) && ((target == PSTATE_ID_CLUSTER_IDLE) || |
| 99 | (target == PSTATE_ID_CLUSTER_POWERDN))) { |
| 100 | return target; |
| 101 | } |
| 102 | |
| 103 | /* System Suspend */ |
| 104 | if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && |
| 105 | (target == PSTATE_ID_SOC_POWERDN)) |
| 106 | return PSTATE_ID_SOC_POWERDN; |
| 107 | |
| 108 | /* default state */ |
| 109 | return PSCI_LOCAL_STATE_RUN; |
| 110 | } |
| 111 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 112 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 113 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 114 | u_register_t mpidr = read_mpidr(); |
| 115 | const plat_local_state_t *pwr_domain_state = |
| 116 | target_state->pwr_domain_state; |
| 117 | unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; |
| 118 | unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; |
| 119 | unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 120 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 121 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 122 | |
Harvey Hsieh | 20e9fef | 2016-12-28 21:53:18 +0800 | [diff] [blame] | 123 | assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || |
| 124 | (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); |
| 125 | assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || |
| 126 | (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 127 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 128 | /* suspend the entire soc */ |
| 129 | tegra_fc_soc_powerdn(mpidr); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 130 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 131 | } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 132 | |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 133 | assert(stateid_afflvl0 == PSTATE_ID_CLUSTER_IDLE); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 134 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 135 | /* Prepare for cluster idle */ |
| 136 | tegra_fc_cluster_idle(mpidr); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 137 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 138 | } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 139 | |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 140 | assert(stateid_afflvl0 == PSTATE_ID_CLUSTER_POWERDN); |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 141 | |
| 142 | /* Prepare for cluster powerdn */ |
| 143 | tegra_fc_cluster_powerdn(mpidr); |
| 144 | |
| 145 | } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { |
| 146 | |
| 147 | /* Prepare for cpu powerdn */ |
| 148 | tegra_fc_cpu_powerdn(mpidr); |
| 149 | |
| 150 | } else { |
| 151 | ERROR("%s: Unknown state id\n", __func__); |
| 152 | return PSCI_E_NOT_SUPPORTED; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 153 | } |
| 154 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 155 | return PSCI_E_SUCCESS; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 156 | } |
| 157 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 158 | int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 159 | { |
Varun Wadekar | bc78744 | 2015-07-27 13:00:50 +0530 | [diff] [blame] | 160 | uint32_t val; |
| 161 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 162 | /* |
| 163 | * Check if we are exiting from SOC_POWERDN. |
| 164 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 165 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
| 166 | PLAT_SYS_SUSPEND_STATE_ID) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 167 | |
| 168 | /* |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 169 | * Lock scratch registers which hold the CPU vectors |
| 170 | */ |
| 171 | tegra_pmc_lock_cpu_vectors(); |
| 172 | |
| 173 | /* |
Varun Wadekar | bc78744 | 2015-07-27 13:00:50 +0530 | [diff] [blame] | 174 | * Enable WRAP to INCR burst type conversions for |
| 175 | * incoming requests on the AXI slave ports. |
| 176 | */ |
| 177 | val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); |
| 178 | val &= ~ENABLE_UNSUP_TX_ERRORS; |
| 179 | val |= ENABLE_WRAP_TO_INCR_BURSTS; |
| 180 | mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); |
| 181 | |
| 182 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 183 | * Restore Boot and Power Management Processor (BPMP) reset |
| 184 | * address and reset it. |
| 185 | */ |
| 186 | tegra_fc_reset_bpmp(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | /* |
| 190 | * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's |
| 191 | * used for power management and boot purposes. Inform the BPMP that |
| 192 | * we have completed the cluster power up. |
| 193 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 194 | tegra_fc_lock_active_cluster(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 195 | |
| 196 | return PSCI_E_SUCCESS; |
| 197 | } |
| 198 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 199 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 200 | { |
| 201 | int cpu = mpidr & MPIDR_CPU_MASK; |
Varun Wadekar | 071b787 | 2015-07-08 17:42:02 +0530 | [diff] [blame] | 202 | uint32_t mask = CPU_CORE_RESET_MASK << cpu; |
| 203 | |
| 204 | /* Deassert CPU reset signals */ |
| 205 | mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 206 | |
| 207 | /* Turn on CPU using flow controller or PMC */ |
| 208 | if (cpu_powergate_mask[cpu] == 0) { |
| 209 | tegra_pmc_cpu_on(cpu); |
| 210 | cpu_powergate_mask[cpu] = 1; |
| 211 | } else { |
| 212 | tegra_fc_cpu_on(cpu); |
| 213 | } |
| 214 | |
| 215 | return PSCI_E_SUCCESS; |
| 216 | } |
| 217 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 218 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 219 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 220 | tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 221 | return PSCI_E_SUCCESS; |
| 222 | } |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 223 | |
| 224 | int tegra_soc_prepare_system_reset(void) |
| 225 | { |
| 226 | /* |
| 227 | * Set System Clock (SCLK) to POR default so that the clock source |
| 228 | * for the PMC APB clock would not be changed due to system reset. |
| 229 | */ |
| 230 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, |
| 231 | SCLK_BURST_POLICY_DEFAULT); |
| 232 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); |
| 233 | |
| 234 | /* Wait 1 ms to make sure clock source/device logic is stabilized. */ |
| 235 | mdelay(1); |
| 236 | |
| 237 | return PSCI_E_SUCCESS; |
| 238 | } |