| Varun Wadekar | 28463b9 | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 1 | /* |
| Varun Wadekar | d43583c | 2016-02-22 11:09:41 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
| Varun Wadekar | 28463b9 | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Varun Wadekar | 28463b9 | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <assert_macros.S> |
| 10 | #include <denver.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| Varun Wadekar | d43583c | 2016-02-22 11:09:41 -0800 | [diff] [blame] | 14 | .global denver_disable_dco |
| 15 | |
| Varun Wadekar | 28463b9 | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 16 | /* --------------------------------------------- |
| 17 | * Disable debug interfaces |
| 18 | * --------------------------------------------- |
| 19 | */ |
| 20 | func denver_disable_ext_debug |
| 21 | mov x0, #1 |
| 22 | msr osdlr_el1, x0 |
| 23 | isb |
| 24 | dsb sy |
| 25 | ret |
| 26 | endfunc denver_disable_ext_debug |
| 27 | |
| 28 | /* ---------------------------------------------------- |
| 29 | * Enable dynamic code optimizer (DCO) |
| 30 | * ---------------------------------------------------- |
| 31 | */ |
| 32 | func denver_enable_dco |
| 33 | mrs x0, mpidr_el1 |
| 34 | and x0, x0, #0xF |
| 35 | mov x1, #1 |
| 36 | lsl x1, x1, x0 |
| 37 | msr s3_0_c15_c0_2, x1 |
| Varun Wadekar | 28463b9 | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 38 | ret |
| 39 | endfunc denver_enable_dco |
| 40 | |
| 41 | /* ---------------------------------------------------- |
| 42 | * Disable dynamic code optimizer (DCO) |
| 43 | * ---------------------------------------------------- |
| 44 | */ |
| 45 | func denver_disable_dco |
| 46 | |
| 47 | /* turn off background work */ |
| 48 | mrs x0, mpidr_el1 |
| 49 | and x0, x0, #0xF |
| 50 | mov x1, #1 |
| 51 | lsl x1, x1, x0 |
| 52 | lsl x2, x1, #16 |
| 53 | msr s3_0_c15_c0_2, x2 |
| 54 | isb |
| 55 | |
| 56 | /* wait till the background work turns off */ |
| 57 | 1: mrs x2, s3_0_c15_c0_2 |
| 58 | lsr x2, x2, #32 |
| 59 | and w2, w2, 0xFFFF |
| 60 | and x2, x2, x1 |
| 61 | cbnz x2, 1b |
| 62 | |
| 63 | ret |
| 64 | endfunc denver_disable_dco |
| 65 | |
| 66 | /* ------------------------------------------------- |
| 67 | * The CPU Ops reset function for Denver. |
| 68 | * ------------------------------------------------- |
| 69 | */ |
| 70 | func denver_reset_func |
| 71 | |
| 72 | mov x19, x30 |
| 73 | |
| 74 | /* ---------------------------------------------------- |
| 75 | * Enable dynamic code optimizer (DCO) |
| 76 | * ---------------------------------------------------- |
| 77 | */ |
| 78 | bl denver_enable_dco |
| 79 | |
| 80 | ret x19 |
| 81 | endfunc denver_reset_func |
| 82 | |
| 83 | /* ---------------------------------------------------- |
| 84 | * The CPU Ops core power down function for Denver. |
| 85 | * ---------------------------------------------------- |
| 86 | */ |
| 87 | func denver_core_pwr_dwn |
| 88 | |
| 89 | mov x19, x30 |
| 90 | |
| Varun Wadekar | 28463b9 | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 91 | /* --------------------------------------------- |
| 92 | * Force the debug interfaces to be quiescent |
| 93 | * --------------------------------------------- |
| 94 | */ |
| 95 | bl denver_disable_ext_debug |
| 96 | |
| 97 | ret x19 |
| 98 | endfunc denver_core_pwr_dwn |
| 99 | |
| 100 | /* ------------------------------------------------------- |
| 101 | * The CPU Ops cluster power down function for Denver. |
| 102 | * ------------------------------------------------------- |
| 103 | */ |
| 104 | func denver_cluster_pwr_dwn |
| 105 | ret |
| 106 | endfunc denver_cluster_pwr_dwn |
| 107 | |
| 108 | /* --------------------------------------------- |
| 109 | * This function provides Denver specific |
| 110 | * register information for crash reporting. |
| 111 | * It needs to return with x6 pointing to |
| 112 | * a list of register names in ascii and |
| 113 | * x8 - x15 having values of registers to be |
| 114 | * reported. |
| 115 | * --------------------------------------------- |
| 116 | */ |
| 117 | .section .rodata.denver_regs, "aS" |
| 118 | denver_regs: /* The ascii list of register names to be reported */ |
| 119 | .asciz "actlr_el1", "" |
| 120 | |
| 121 | func denver_cpu_reg_dump |
| 122 | adr x6, denver_regs |
| 123 | mrs x8, ACTLR_EL1 |
| 124 | ret |
| 125 | endfunc denver_cpu_reg_dump |
| 126 | |
| Varun Wadekar | 3c337a6 | 2015-09-03 17:15:06 +0530 | [diff] [blame] | 127 | declare_cpu_ops denver, DENVER_MIDR_PN0, \ |
| 128 | denver_reset_func, \ |
| 129 | denver_core_pwr_dwn, \ |
| 130 | denver_cluster_pwr_dwn |
| 131 | |
| 132 | declare_cpu_ops denver, DENVER_MIDR_PN1, \ |
| 133 | denver_reset_func, \ |
| 134 | denver_core_pwr_dwn, \ |
| 135 | denver_cluster_pwr_dwn |
| 136 | |
| 137 | declare_cpu_ops denver, DENVER_MIDR_PN2, \ |
| 138 | denver_reset_func, \ |
| 139 | denver_core_pwr_dwn, \ |
| 140 | denver_cluster_pwr_dwn |
| 141 | |
| 142 | declare_cpu_ops denver, DENVER_MIDR_PN3, \ |
| 143 | denver_reset_func, \ |
| 144 | denver_core_pwr_dwn, \ |
| 145 | denver_cluster_pwr_dwn |
| 146 | |
| 147 | declare_cpu_ops denver, DENVER_MIDR_PN4, \ |
| Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 148 | denver_reset_func, \ |
| 149 | denver_core_pwr_dwn, \ |
| 150 | denver_cluster_pwr_dwn |