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git01.mediatek.com / filogic / atf / d43583c68c983dc1bcc2177af311bdd0ef554a1f / . / lib / cpus / aarch64 / denver.S
blob: 3e238a1c19e6c9e4834b4ce0ce5eefa9696b61c3 [file] [log] [blame]
Varun Wadekar28463b92015-07-14 17:11:20 +0530[diff] [blame]1/*
Varun Wadekard43583c2016-02-22 11:09:41 -0800[diff] [blame^]2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Varun Wadekar28463b92015-07-14 17:11:20 +0530[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <assert_macros.S>
34#include <denver.h>
35#include <cpu_macros.S>
36#include <plat_macros.S>
37
Varun Wadekard43583c2016-02-22 11:09:41 -0800[diff] [blame^]38 .global denver_disable_dco
39
Varun Wadekar28463b92015-07-14 17:11:20 +0530[diff] [blame]40 /* ---------------------------------------------
41 * Disable debug interfaces
42 * ---------------------------------------------
43 */
44func denver_disable_ext_debug
45 mov x0, #1
46 msr osdlr_el1, x0
47 isb
48 dsb sy
49 ret
50endfunc denver_disable_ext_debug
51
52 /* ----------------------------------------------------
53 * Enable dynamic code optimizer (DCO)
54 * ----------------------------------------------------
55 */
56func denver_enable_dco
57 mrs x0, mpidr_el1
58 and x0, x0, #0xF
59 mov x1, #1
60 lsl x1, x1, x0
61 msr s3_0_c15_c0_2, x1
62 isb
63 ret
64endfunc denver_enable_dco
65
66 /* ----------------------------------------------------
67 * Disable dynamic code optimizer (DCO)
68 * ----------------------------------------------------
69 */
70func denver_disable_dco
71
72 /* turn off background work */
73 mrs x0, mpidr_el1
74 and x0, x0, #0xF
75 mov x1, #1
76 lsl x1, x1, x0
77 lsl x2, x1, #16
78 msr s3_0_c15_c0_2, x2
79 isb
80
81 /* wait till the background work turns off */
821: mrs x2, s3_0_c15_c0_2
83 lsr x2, x2, #32
84 and w2, w2, 0xFFFF
85 and x2, x2, x1
86 cbnz x2, 1b
87
88 ret
89endfunc denver_disable_dco
90
91 /* -------------------------------------------------
92 * The CPU Ops reset function for Denver.
93 * -------------------------------------------------
94 */
95func denver_reset_func
96
97 mov x19, x30
98
99 /* ----------------------------------------------------
100 * Enable dynamic code optimizer (DCO)
101 * ----------------------------------------------------
102 */
103 bl denver_enable_dco
104
105 ret x19
106endfunc denver_reset_func
107
108 /* ----------------------------------------------------
109 * The CPU Ops core power down function for Denver.
110 * ----------------------------------------------------
111 */
112func denver_core_pwr_dwn
113
114 mov x19, x30
115
Varun Wadekar28463b92015-07-14 17:11:20 +0530[diff] [blame]116 /* ---------------------------------------------
117 * Force the debug interfaces to be quiescent
118 * ---------------------------------------------
119 */
120 bl denver_disable_ext_debug
121
122 ret x19
123endfunc denver_core_pwr_dwn
124
125 /* -------------------------------------------------------
126 * The CPU Ops cluster power down function for Denver.
127 * -------------------------------------------------------
128 */
129func denver_cluster_pwr_dwn
130 ret
131endfunc denver_cluster_pwr_dwn
132
133 /* ---------------------------------------------
134 * This function provides Denver specific
135 * register information for crash reporting.
136 * It needs to return with x6 pointing to
137 * a list of register names in ascii and
138 * x8 - x15 having values of registers to be
139 * reported.
140 * ---------------------------------------------
141 */
142.section .rodata.denver_regs, "aS"
143denver_regs: /* The ascii list of register names to be reported */
144 .asciz "actlr_el1", ""
145
146func denver_cpu_reg_dump
147 adr x6, denver_regs
148 mrs x8, ACTLR_EL1
149 ret
150endfunc denver_cpu_reg_dump
151
Varun Wadekar3c337a62015-09-03 17:15:06 +0530[diff] [blame]152declare_cpu_ops denver, DENVER_MIDR_PN0, \
153 denver_reset_func, \
154 denver_core_pwr_dwn, \
155 denver_cluster_pwr_dwn
156
157declare_cpu_ops denver, DENVER_MIDR_PN1, \
158 denver_reset_func, \
159 denver_core_pwr_dwn, \
160 denver_cluster_pwr_dwn
161
162declare_cpu_ops denver, DENVER_MIDR_PN2, \
163 denver_reset_func, \
164 denver_core_pwr_dwn, \
165 denver_cluster_pwr_dwn
166
167declare_cpu_ops denver, DENVER_MIDR_PN3, \
168 denver_reset_func, \
169 denver_core_pwr_dwn, \
170 denver_cluster_pwr_dwn
171
172declare_cpu_ops denver, DENVER_MIDR_PN4, \
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +0000[diff] [blame]173 denver_reset_func, \
174 denver_core_pwr_dwn, \
175 denver_cluster_pwr_dwn