Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | 6077dce | 2016-01-27 11:31:06 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <assert.h> |
| 33 | #include <debug.h> |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 34 | #include <delay_timer.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 35 | #include <mmio.h> |
| 36 | #include <platform.h> |
| 37 | #include <platform_def.h> |
| 38 | #include <psci.h> |
| 39 | #include <pmc.h> |
| 40 | #include <flowctrl.h> |
| 41 | #include <tegra_def.h> |
| 42 | #include <tegra_private.h> |
| 43 | |
Varun Wadekar | 071b787 | 2015-07-08 17:42:02 +0530 | [diff] [blame] | 44 | /* |
| 45 | * Register used to clear CPU reset signals. Each CPU has two reset |
| 46 | * signals: CPU reset (3:0) and Core reset (19:16). |
| 47 | */ |
| 48 | #define CPU_CMPLX_RESET_CLR 0x454 |
| 49 | #define CPU_CORE_RESET_MASK 0x10001 |
| 50 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 51 | /* Clock and Reset controller registers for system clock's settings */ |
| 52 | #define SCLK_RATE 0x30 |
| 53 | #define SCLK_BURST_POLICY 0x28 |
| 54 | #define SCLK_BURST_POLICY_DEFAULT 0x10000000 |
| 55 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 56 | static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
| 57 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 58 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 59 | psci_power_state_t *req_state) |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 60 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 61 | int state_id = psci_get_pstate_id(power_state); |
| 62 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 63 | /* Sanity check the requested state id */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 64 | switch (state_id) { |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 65 | case PSTATE_ID_CORE_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 66 | /* |
| 67 | * Core powerdown request only for afflvl 0 |
| 68 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 69 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; |
| 70 | |
| 71 | break; |
| 72 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 73 | case PSTATE_ID_CLUSTER_IDLE: |
| 74 | case PSTATE_ID_CLUSTER_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 75 | /* |
| 76 | * Cluster powerdown/idle request only for afflvl 1 |
| 77 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 78 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
Varun Wadekar | dba8007 | 2016-09-01 14:56:17 -0700 | [diff] [blame] | 79 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 80 | |
| 81 | break; |
| 82 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 83 | case PSTATE_ID_SOC_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 84 | /* |
| 85 | * System powerdown request only for afflvl 2 |
| 86 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 87 | for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) |
| 88 | req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
| 89 | |
| 90 | req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = |
| 91 | PLAT_SYS_SUSPEND_STATE_ID; |
| 92 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 93 | break; |
| 94 | |
| 95 | default: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 96 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
| 97 | return PSCI_E_INVALID_PARAMS; |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | return PSCI_E_SUCCESS; |
| 101 | } |
| 102 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 103 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 104 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 105 | u_register_t mpidr = read_mpidr(); |
| 106 | const plat_local_state_t *pwr_domain_state = |
| 107 | target_state->pwr_domain_state; |
| 108 | unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; |
| 109 | unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; |
| 110 | unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 111 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 112 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 113 | |
Harvey Hsieh | 20e9fef | 2016-12-28 21:53:18 +0800 | [diff] [blame] | 114 | assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || |
| 115 | (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); |
| 116 | assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || |
| 117 | (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 118 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 119 | /* suspend the entire soc */ |
| 120 | tegra_fc_soc_powerdn(mpidr); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 121 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 122 | } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 123 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 124 | assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 125 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 126 | /* Prepare for cluster idle */ |
| 127 | tegra_fc_cluster_idle(mpidr); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 128 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 129 | } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 130 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 131 | assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); |
| 132 | |
| 133 | /* Prepare for cluster powerdn */ |
| 134 | tegra_fc_cluster_powerdn(mpidr); |
| 135 | |
| 136 | } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { |
| 137 | |
| 138 | /* Prepare for cpu powerdn */ |
| 139 | tegra_fc_cpu_powerdn(mpidr); |
| 140 | |
| 141 | } else { |
| 142 | ERROR("%s: Unknown state id\n", __func__); |
| 143 | return PSCI_E_NOT_SUPPORTED; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 144 | } |
| 145 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 146 | return PSCI_E_SUCCESS; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 147 | } |
| 148 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 149 | int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 150 | { |
Varun Wadekar | bc78744 | 2015-07-27 13:00:50 +0530 | [diff] [blame] | 151 | uint32_t val; |
| 152 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 153 | /* |
| 154 | * Check if we are exiting from SOC_POWERDN. |
| 155 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 156 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
| 157 | PLAT_SYS_SUSPEND_STATE_ID) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 158 | |
| 159 | /* |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 160 | * Lock scratch registers which hold the CPU vectors |
| 161 | */ |
| 162 | tegra_pmc_lock_cpu_vectors(); |
| 163 | |
| 164 | /* |
Varun Wadekar | bc78744 | 2015-07-27 13:00:50 +0530 | [diff] [blame] | 165 | * Enable WRAP to INCR burst type conversions for |
| 166 | * incoming requests on the AXI slave ports. |
| 167 | */ |
| 168 | val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); |
| 169 | val &= ~ENABLE_UNSUP_TX_ERRORS; |
| 170 | val |= ENABLE_WRAP_TO_INCR_BURSTS; |
| 171 | mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); |
| 172 | |
| 173 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 174 | * Restore Boot and Power Management Processor (BPMP) reset |
| 175 | * address and reset it. |
| 176 | */ |
| 177 | tegra_fc_reset_bpmp(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | /* |
| 181 | * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's |
| 182 | * used for power management and boot purposes. Inform the BPMP that |
| 183 | * we have completed the cluster power up. |
| 184 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 185 | tegra_fc_lock_active_cluster(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 186 | |
| 187 | return PSCI_E_SUCCESS; |
| 188 | } |
| 189 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 190 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 191 | { |
| 192 | int cpu = mpidr & MPIDR_CPU_MASK; |
Varun Wadekar | 071b787 | 2015-07-08 17:42:02 +0530 | [diff] [blame] | 193 | uint32_t mask = CPU_CORE_RESET_MASK << cpu; |
| 194 | |
| 195 | /* Deassert CPU reset signals */ |
| 196 | mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 197 | |
| 198 | /* Turn on CPU using flow controller or PMC */ |
| 199 | if (cpu_powergate_mask[cpu] == 0) { |
| 200 | tegra_pmc_cpu_on(cpu); |
| 201 | cpu_powergate_mask[cpu] = 1; |
| 202 | } else { |
| 203 | tegra_fc_cpu_on(cpu); |
| 204 | } |
| 205 | |
| 206 | return PSCI_E_SUCCESS; |
| 207 | } |
| 208 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 209 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 210 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 211 | tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 212 | return PSCI_E_SUCCESS; |
| 213 | } |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 214 | |
| 215 | int tegra_soc_prepare_system_reset(void) |
| 216 | { |
| 217 | /* |
| 218 | * Set System Clock (SCLK) to POR default so that the clock source |
| 219 | * for the PMC APB clock would not be changed due to system reset. |
| 220 | */ |
| 221 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, |
| 222 | SCLK_BURST_POLICY_DEFAULT); |
| 223 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); |
| 224 | |
| 225 | /* Wait 1 ms to make sure clock source/device logic is stabilized. */ |
| 226 | mdelay(1); |
| 227 | |
| 228 | return PSCI_E_SUCCESS; |
| 229 | } |