blob: b7397ba3e733cb5a4a21041478a2259bc664acb8 [file] [log] [blame]
Jiafei Pana07047b2022-02-18 15:27:45 +08001/*
2 * Copyright 2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <errno.h>
8
9#include <common/debug.h>
10#include <ddr.h>
11#include <utils.h>
12
13#include <errata.h>
14#include <platform_def.h>
15
16#ifdef CONFIG_STATIC_DDR
17#error No static value defined
18#endif
19
20static const struct rc_timing rce[] = {
21 {U(1600), U(8), U(8)},
22 {U(1867), U(8), U(8)},
23 {U(2134), U(8), U(9)},
24 {}
25};
26
27static const struct board_timing udimm[] = {
28 {U(0x04), rce, U(0x01020307), U(0x08090b06)},
29};
30
31int ddr_board_options(struct ddr_info *priv)
32{
33 int ret;
34 struct memctl_opt *popts = &priv->opt;
35
36 if (popts->rdimm != 0) {
37 debug("RDIMM parameters not set.\n");
38 return -EINVAL;
39 }
40
41 ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm));
42 if (ret != 0) {
43 return ret;
44 }
45
46 popts->addr_hash = 1;
47 popts->cpo_sample = U(0x7b);
48 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
49 DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
50 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
51 DDR_CDR2_VREF_TRAIN_EN |
52 DDR_CDR2_VREF_RANGE_2;
53
54 return 0;
55}
56
57long long init_ddr(void)
58{
59 int spd_addr[] = { NXP_SPD_EEPROM0 };
60 struct ddr_info info;
61 struct sysinfo sys;
62 long long dram_size;
63
64 zeromem(&sys, sizeof(sys));
65 get_clocks(&sys);
66 debug("platform clock %lu\n", sys.freq_platform);
67 debug("DDR PLL %lu\n", sys.freq_ddr_pll0);
68
69 zeromem(&info, sizeof(struct ddr_info));
70 info.num_ctlrs = NUM_OF_DDRC;
71 info.dimm_on_ctlr = DDRC_NUM_DIMM;
72 info.clk = get_ddr_freq(&sys, 0);
73 info.spd_addr = spd_addr;
74 info.ddr[0] = (void *)NXP_DDR_ADDR;
75
76 dram_size = dram_init(&info);
77 if (dram_size < 0) {
78 ERROR("DDR init failed.\n");
79 }
80
81 erratum_a008850_post();
82
83 return dram_size;
84}