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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
Tanmay Shahfdae9e82022-08-26 15:06:00 -07003 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
Akshay Belsare589ccce2023-05-08 19:00:53 +05304 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05305 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include <assert.h>
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053010#include <errno.h>
Prasad Kummari536e1102023-06-22 10:50:02 +053011
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <bl31/bl31.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070015#include <drivers/arm/dcc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <drivers/arm/pl011.h>
17#include <drivers/console.h>
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070018#include <lib/mmio.h>
Michal Simek058251a2023-04-13 13:19:11 +020019#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <plat/common/platform.h>
Prasad Kummari536e1102023-06-22 10:50:02 +053021#include <plat_arm.h>
22
Amit Nagal3a7d3042023-07-10 10:32:15 +053023#include <plat_fdt.h>
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070024#include <plat_private.h>
25#include <plat_startup.h>
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +053026#include "pm_api_sys.h"
Prasad Kummari536e1102023-06-22 10:50:02 +053027#include "pm_client.h"
28#include <pm_ipi.h>
29#include <versal_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000030
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053031static entry_point_info_t bl32_image_ep_info;
32static entry_point_info_t bl33_image_ep_info;
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053033
34/*
35 * Return a pointer to the 'entry_point_info' structure of the next image for
36 * the security state specified. BL33 corresponds to the non-secure image type
37 * while BL32 corresponds to the secure image type. A NULL pointer is returned
38 * if the image does not exist.
39 */
40entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
41{
42 assert(sec_state_is_valid(type));
43
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070044 if (type == NON_SECURE) {
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053045 return &bl33_image_ep_info;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070046 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053047
48 return &bl32_image_ep_info;
49}
50
51/*
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070052 * Set the build time defaults,if we can't find any config data.
53 */
54static inline void bl31_set_default_config(void)
55{
Abhyuday Godhasarac0c49e52021-08-24 07:39:41 -070056 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
57 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry();
58 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint();
59 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
60 DISABLE_ALL_EXCEPTIONS);
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070061}
62
63/*
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053064 * Perform any BL31 specific platform actions. Here is an opportunity to copy
65 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
66 * are lost (potentially). This needs to be done before the MMU is initialized
67 * so that the memory layout can be used while creating page tables.
68 */
69void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
70 u_register_t arg2, u_register_t arg3)
71{
Prasad Kummarie0783112023-04-26 11:02:07 +053072 uint64_t tfa_handoff_addr;
Prasad Kummari07795fa2023-06-08 21:36:38 +053073 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE;
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +053074 enum pm_ret_status ret_status;
Prasad Kummari07795fa2023-06-08 21:36:38 +053075 uint64_t addr[HANDOFF_PARAMS_MAX_SIZE];
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053076
Venkatesh Yadav Abbarapue91b4c22021-12-19 21:36:23 -070077 if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) {
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070078 static console_t versal_runtime_console;
79 /* Initialize the console to provide early debug support */
Venkatesh Yadav Abbarapu2cefbcd2022-07-31 14:05:40 +053080 int32_t rc = console_pl011_register((uintptr_t)VERSAL_UART_BASE,
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053081 (uint32_t)VERSAL_UART_CLOCK,
82 (uint32_t)VERSAL_UART_BAUDRATE,
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070083 &versal_runtime_console);
84 if (rc == 0) {
85 panic();
86 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053087
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053088 console_set_scope(&versal_runtime_console, (uint32_t)(CONSOLE_FLAG_BOOT |
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -070089 CONSOLE_FLAG_RUNTIME));
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070090 } else if (VERSAL_CONSOLE_IS(dcc)) {
91 /* Initialize the dcc console for debug */
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053092 int32_t rc = console_dcc_register();
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070093 if (rc == 0) {
94 panic();
95 }
Abhyuday Godhasara4c1a7052021-08-11 02:52:35 -070096 } else {
97 NOTICE("BL31: Did not register for any console.\n");
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070098 }
Abhyuday Godhasara4c1a7052021-08-11 02:52:35 -070099
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530100 /* Initialize the platform config for future decision making */
101 versal_config_setup();
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530102
Akshay Belsare589ccce2023-05-08 19:00:53 +0530103 /* Get platform related information */
104 board_detection();
105
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530106 /*
107 * Do initial security configuration to allow DRAM/device access. On
108 * Base VERSAL only DRAM security is programmable (via TrustZone), but
109 * other platforms might have more programmable security devices
110 * present.
111 */
112
113 /* Populate common information for BL32 and BL33 */
114 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
115 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
116 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
117 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
118
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +0530119 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS,
120 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size);
121 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
122 if (ret_status == PM_RET_SUCCESS) {
123 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status);
Prasad Kummarie0783112023-04-26 11:02:07 +0530124 tfa_handoff_addr = (uintptr_t)&addr;
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +0530125 } else {
Prasad Kummarie0783112023-04-26 11:02:07 +0530126 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read tfa_handoff_addr from reg\n");
127 tfa_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4);
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +0530128 }
129
Prasad Kummari07795fa2023-06-08 21:36:38 +0530130 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info,
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700131 &bl33_image_ep_info,
Prasad Kummarie0783112023-04-26 11:02:07 +0530132 tfa_handoff_addr);
Prasad Kummari07795fa2023-06-08 21:36:38 +0530133 if (ret == XBL_HANDOFF_NO_STRUCT || ret == XBL_HANDOFF_INVAL_STRUCT) {
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700134 bl31_set_default_config();
Prasad Kummari07795fa2023-06-08 21:36:38 +0530135 } else if (ret == XBL_HANDOFF_TOO_MANY_PARTS) {
Venkatesh Yadav Abbarapu39fdc0a2022-03-03 01:58:36 -0700136 ERROR("BL31: Error too many partitions %u\n", ret);
Prasad Kummari07795fa2023-06-08 21:36:38 +0530137 } else if (ret != XBL_HANDOFF_SUCCESS) {
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700138 panic();
Abhyuday Godhasara4c1a7052021-08-11 02:52:35 -0700139 } else {
Akshay Belsaree3511ae2023-01-11 11:45:25 +0530140 INFO("BL31: PLM to TF-A handover success %u\n", ret);
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700141 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530142
143 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
144 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
145}
146
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700147static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530148
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700149int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530150{
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700151 static uint32_t index;
152 uint32_t i;
153
154 /* Validate 'handler' and 'id' parameters */
155 if (handler == NULL || index >= MAX_INTR_EL3) {
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530156 return -EINVAL;
157 }
158
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700159 /* Check if a handler has already been registered */
160 for (i = 0; i < index; i++) {
161 if (id == type_el3_interrupt_table[i].id) {
162 return -EALREADY;
163 }
164 }
165
166 type_el3_interrupt_table[index].id = id;
167 type_el3_interrupt_table[index].handler = handler;
168
169 index++;
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530170
171 return 0;
172}
173
174static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
175 void *handle, void *cookie)
176{
177 uint32_t intr_id;
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700178 uint32_t i;
179 interrupt_type_handler_t handler = NULL;
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530180
181 intr_id = plat_ic_get_pending_interrupt_id();
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530182
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700183 for (i = 0; i < MAX_INTR_EL3; i++) {
184 if (intr_id == type_el3_interrupt_table[i].id) {
185 handler = type_el3_interrupt_table[i].handler;
186 }
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530187 }
188
Michal Simek5e2f5962022-09-13 11:48:53 +0200189 if (handler != NULL) {
190 return handler(intr_id, flags, handle, cookie);
191 }
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700192
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530193 return 0;
194}
Amit Nagal3a7d3042023-07-10 10:32:15 +0530195
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530196void bl31_platform_setup(void)
197{
Amit Nagal3a7d3042023-07-10 10:32:15 +0530198 prepare_dtb();
199
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530200 /* Initialize the gic cpu and distributor interfaces */
201 plat_versal_gic_driver_init();
202 plat_versal_gic_init();
203}
204
205void bl31_plat_runtime_setup(void)
206{
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530207 uint64_t flags = 0;
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700208 int32_t rc;
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530209
210 set_interrupt_rm_flag(flags, NON_SECURE);
211 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
212 rdo_el3_interrupt_handler, flags);
Abhyuday Godhasarabacbdee2021-08-20 00:27:03 -0700213 if (rc != 0) {
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530214 panic();
215 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530216}
217
218/*
219 * Perform the very early platform specific architectural setup here.
220 */
221void bl31_plat_arch_setup(void)
222{
Tejas Patel54d13192019-02-27 18:44:55 +0530223 plat_arm_interconnect_init();
224 plat_arm_interconnect_enter_coherency();
225
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530226 const mmap_region_t bl_regions[] = {
Amit Nagalc1248e82023-09-04 21:53:59 -1200227#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE) && \
228 (!defined(PLAT_XLAT_TABLES_DYNAMIC)))
Amit Nagal3a7d3042023-07-10 10:32:15 +0530229 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
230 MT_MEMORY | MT_RW | MT_NS),
231#endif
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530232 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
233 MT_MEMORY | MT_RW | MT_SECURE),
234 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
235 MT_CODE | MT_SECURE),
236 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
237 MT_RO_DATA | MT_SECURE),
238 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
239 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
240 MT_DEVICE | MT_RW | MT_SECURE),
241 {0}
242 };
243
244 setup_page_tables(bl_regions, plat_versal_get_mmap());
Michal Simek058251a2023-04-13 13:19:11 +0200245 enable_mmu(0);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530246}