blob: 6c53bc11c230e41d0a472b16e3e1951bb4acb1ce [file] [log] [blame]
Jit Loon Lima7f54942023-05-17 12:26:11 +08001/*
2 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <errno.h>
9#include <stdbool.h>
10#include <string.h>
11
12#include <arch_helpers.h>
13#include <common/debug.h>
14#include <drivers/cadence/cdns_sdmmc.h>
15#include <drivers/delay_timer.h>
16#include <lib/mmio.h>
17#include <lib/utils.h>
18
19#include "combophy.h"
20#include "sdmmc/sdmmc.h"
21
22/* Temp assigned handoff data, need to remove when SDM up and run. */
23void config_nand(handoff *hoff_ptr)
24{
25 /* This is hardcoded input value for Combo PHY and SD host controller. */
26 hoff_ptr->peripheral_pwr_gate_array = 0x40;
27
28}
29
30/* DFI configuration */
31int dfi_select(handoff *hoff_ptr)
32{
33 uint32_t data = 0;
34
35 /* Temp assigned handoff data, need to remove when SDM up and run. */
36 handoff reverse_handoff_ptr;
37
38 /* Temp assigned handoff data, need to remove when SDM up and run. */
39 config_nand(&reverse_handoff_ptr);
40
41 if (((reverse_handoff_ptr.peripheral_pwr_gate_array) & PERIPHERAL_SDMMC_MASK) == 0U) {
42 ERROR("SDMMC/NAND is not set properly\n");
43 return -ENXIO;
44 }
45
46 mmio_setbits_32(SOCFPGA_SYSMGR(DFI_INTF),
47 (((reverse_handoff_ptr.peripheral_pwr_gate_array) &
48 PERIPHERAL_SDMMC_MASK) >> PERIPHERAL_SDMMC_OFFSET));
49 data = mmio_read_32(SOCFPGA_SYSMGR(DFI_INTF));
50 if ((data & DFI_INTF_MASK) != (((reverse_handoff_ptr.peripheral_pwr_gate_array) &
51 PERIPHERAL_SDMMC_MASK) >> PERIPHERAL_SDMMC_OFFSET)) {
52 ERROR("DFI is not set properly\n");
53 return -ENXIO;
54 }
55
56 return 0;
57}
58
59int combo_phy_init(handoff *hoff_ptr)
60{
61 /* SDMMC/NAND DFI selection based on system manager DFI register */
62 int ret = dfi_select(hoff_ptr);
63
64 if (ret != 0U) {
65 ERROR("DFI configuration failed\n");
66 return ret;
67 }
68
69 return 0;
70}