Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023-2024, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 8 | #include <dt-bindings/interrupt-controller/irq.h> |
| 9 | |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 10 | #define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) |
| 11 | #define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) |
| 12 | |
| 13 | /* All perf is normalized against the big core */ |
| 14 | #define BIG_CAPACITY 1024 |
| 15 | |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 16 | #if TARGET_PLATFORM <= 2 |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 17 | #if TARGET_FLAVOUR_FVP |
| 18 | #define LIT_CAPACITY 406 |
| 19 | #define MID_CAPACITY 912 |
| 20 | #else /* TARGET_FLAVOUR_FPGA */ |
| 21 | #define LIT_CAPACITY 280 |
| 22 | #define MID_CAPACITY 775 |
| 23 | /* this is an area optimized configuration of the big core */ |
| 24 | #define BIG2_CAPACITY 930 |
| 25 | #endif /* TARGET_FLAVOUR_FPGA */ |
| 26 | |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 27 | #define INT_MBOX_RX 317 |
| 28 | #define MHU_TX_ADDR(pref) pref##45000000 /* hex */ |
| 29 | #define MHU_RX_ADDR(pref) pref##45010000 /* hex */ |
| 30 | #define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ |
| 31 | #define UARTCLK_FREQ 5000000 |
| 32 | #elif TARGET_PLATFORM == 3 |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 33 | |
| 34 | #define LIT_CAPACITY 239 |
| 35 | #define MID_CAPACITY 686 |
| 36 | |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 37 | #define INT_MBOX_RX 300 |
| 38 | #define MHU_TX_ADDR(pref) pref##46040000 /* hex */ |
| 39 | #define MHU_RX_ADDR(pref) pref##46140000 /* hex */ |
| 40 | #define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ |
| 41 | #define UARTCLK_FREQ 3750000 |
| 42 | #endif /* TARGET_PLATFORM == 3 */ |
| 43 | |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 44 | #if TARGET_FLAVOUR_FVP |
| 45 | #define STDOUT_PATH "serial0:115200n8" |
| 46 | #define GIC_CTRL_ADDR 2c010000 |
| 47 | #define GIC_GICR_OFFSET 0x200000 |
| 48 | #define UART_OFFSET 0x1000 |
| 49 | #define VENCODER_TIMING_CLK 25175000 |
| 50 | #define VENCODER_TIMING \ |
| 51 | clock-frequency = <VENCODER_TIMING_CLK>; \ |
| 52 | hactive = <640>; \ |
| 53 | vactive = <480>; \ |
| 54 | hfront-porch = <16>; \ |
| 55 | hback-porch = <48>; \ |
| 56 | hsync-len = <96>; \ |
| 57 | vfront-porch = <10>; \ |
| 58 | vback-porch = <33>; \ |
| 59 | vsync-len = <2> |
| 60 | #define ETH_COMPATIBLE "smsc,lan91c111" |
| 61 | #define MMC_REMOVABLE cd-gpios = <&sysreg 0 0> |
| 62 | |
| 63 | #else /* TARGET_FLAVOUR_FPGA */ |
| 64 | |
| 65 | #define STDOUT_PATH "serial0:38400n8" |
| 66 | #define GIC_CTRL_ADDR 30000000 |
| 67 | #define GIC_GICR_OFFSET 0x1000000 |
| 68 | #define UART_OFFSET 0x10000 |
| 69 | /* 1440x3200@120 framebuffer */ |
| 70 | #define VENCODER_TIMING_CLK 836000000 |
| 71 | #define VENCODER_TIMING \ |
| 72 | clock-frequency = <VENCODER_TIMING_CLK>; \ |
| 73 | hactive = <1440>; \ |
| 74 | vactive = <3200>; \ |
| 75 | hfront-porch = <136>; \ |
| 76 | hback-porch = <296>; \ |
| 77 | hsync-len = <160>; \ |
| 78 | vfront-porch = <3>; \ |
| 79 | vback-porch = <217>; \ |
| 80 | vsync-len = <10> |
| 81 | #define ETH_COMPATIBLE "smsc,lan9115" |
| 82 | #define MMC_REMOVABLE non-removable |
| 83 | #endif /* TARGET_FLAVOUR_FPGA */ |
| 84 | |
| 85 | /* Use SCMI controlled clocks */ |
| 86 | #if TC_DPU_USE_SCMI_CLK |
| 87 | #define DPU_CLK_ATTR1 \ |
| 88 | clocks = <&scmi_clk 0>; \ |
| 89 | clock-names = "aclk" |
| 90 | |
| 91 | #define DPU_CLK_ATTR2 \ |
| 92 | clocks = <&scmi_clk 1>; \ |
| 93 | clock-names = "pxclk" |
| 94 | |
| 95 | #define DPU_CLK_ATTR3 \ |
| 96 | clocks = <&scmi_clk 2>; \ |
| 97 | clock-names = "pxclk" \ |
| 98 | /* Use fixed clocks */ |
| 99 | #else /* !TC_DPU_USE_SCMI_CLK */ |
| 100 | #define DPU_CLK_ATTR1 \ |
| 101 | clocks = <&dpu_aclk>; \ |
| 102 | clock-names = "aclk" |
| 103 | |
| 104 | #define DPU_CLK_ATTR2 \ |
| 105 | clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ |
| 106 | clock-names = "pxclk", "aclk" |
| 107 | |
| 108 | #define DPU_CLK_ATTR3 DPU_CLK_ATTR2 |
| 109 | #endif /* !TC_DPU_USE_SCMI_CLK */ |
| 110 | |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 111 | / { |
| 112 | #if TARGET_PLATFORM <= 2 |
| 113 | cmn-pmu { |
| 114 | compatible = "arm,ci-700"; |
| 115 | reg = <0x0 0x50000000 0x0 0x10000000>; |
| 116 | interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>; |
| 117 | }; |
| 118 | #endif /* TARGET_PLATFORM <= 2 */ |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 119 | |
| 120 | #if !TC_DPU_USE_SCMI_CLK |
| 121 | dpu_aclk: dpu_aclk { |
| 122 | compatible = "fixed-clock"; |
| 123 | #clock-cells = <0>; |
| 124 | clock-frequency = <VENCODER_TIMING_CLK>; |
| 125 | clock-output-names = "fpga:dpu_aclk"; |
| 126 | }; |
| 127 | |
| 128 | dpu_pixel_clk: dpu-pixel-clk { |
| 129 | compatible = "fixed-clock"; |
| 130 | #clock-cells = <0>; |
| 131 | clock-frequency = <VENCODER_TIMING_CLK>; |
| 132 | clock-output-names = "pxclk"; |
| 133 | }; |
| 134 | #endif /* !TC_DPU_USE_SCMI_CLK */ |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 135 | }; |