blob: 1b93ab2c71901b9570f956d2c7f3ecf4f778e90f [file] [log] [blame]
Yann Gautierbb836ee2018-07-16 17:55:07 +02001/*
2 * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7
8#ifndef __STPMU1_H__
9#define __STPMU1_H__
10
11#include <stm32_i2c.h>
12#include <utils_def.h>
13
14#define TURN_ON_REG 0x1U
15#define TURN_OFF_REG 0x2U
16#define ICC_LDO_TURN_OFF_REG 0x3U
17#define ICC_BUCK_TURN_OFF_REG 0x4U
18#define RESET_STATUS_REG 0x5U
19#define VERSION_STATUS_REG 0x6U
20#define MAIN_CONTROL_REG 0x10U
21#define PADS_PULL_REG 0x11U
22#define BUCK_PULL_DOWN_REG 0x12U
23#define LDO14_PULL_DOWN_REG 0x13U
24#define LDO56_PULL_DOWN_REG 0x14U
25#define VIN_CONTROL_REG 0x15U
26#define PONKEY_TIMER_REG 0x16U
27#define MASK_RANK_BUCK_REG 0x17U
28#define MASK_RESET_BUCK_REG 0x18U
29#define MASK_RANK_LDO_REG 0x19U
30#define MASK_RESET_LDO_REG 0x1AU
31#define WATCHDOG_CONTROL_REG 0x1BU
32#define WATCHDOG_TIMER_REG 0x1CU
33#define BUCK_ICC_TURNOFF_REG 0x1DU
34#define LDO_ICC_TURNOFF_REG 0x1EU
35#define BUCK_APM_CONTROL_REG 0x1FU
36#define BUCK1_CONTROL_REG 0x20U
37#define BUCK2_CONTROL_REG 0x21U
38#define BUCK3_CONTROL_REG 0x22U
39#define BUCK4_CONTROL_REG 0x23U
40#define VREF_DDR_CONTROL_REG 0x24U
41#define LDO1_CONTROL_REG 0x25U
42#define LDO2_CONTROL_REG 0x26U
43#define LDO3_CONTROL_REG 0x27U
44#define LDO4_CONTROL_REG 0x28U
45#define LDO5_CONTROL_REG 0x29U
46#define LDO6_CONTROL_REG 0x2AU
47#define BUCK1_PWRCTRL_REG 0x30U
48#define BUCK2_PWRCTRL_REG 0x31U
49#define BUCK3_PWRCTRL_REG 0x32U
50#define BUCK4_PWRCTRL_REG 0x33U
51#define VREF_DDR_PWRCTRL_REG 0x34U
52#define LDO1_PWRCTRL_REG 0x35U
53#define LDO2_PWRCTRL_REG 0x36U
54#define LDO3_PWRCTRL_REG 0x37U
55#define LDO4_PWRCTRL_REG 0x38U
56#define LDO5_PWRCTRL_REG 0x39U
57#define LDO6_PWRCTRL_REG 0x3AU
58#define FREQUENCY_SPREADING_REG 0x3BU
59#define USB_CONTROL_REG 0x40U
60#define ITLATCH1_REG 0x50U
61#define ITLATCH2_REG 0x51U
62#define ITLATCH3_REG 0x52U
63#define ITLATCH4_REG 0x53U
64#define ITSETLATCH1_REG 0x60U
65#define ITSETLATCH2_REG 0x61U
66#define ITSETLATCH3_REG 0x62U
67#define ITSETLATCH4_REG 0x63U
68#define ITCLEARLATCH1_REG 0x70U
69#define ITCLEARLATCH2_REG 0x71U
70#define ITCLEARLATCH3_REG 0x72U
71#define ITCLEARLATCH4_REG 0x73U
72#define ITMASK1_REG 0x80U
73#define ITMASK2_REG 0x81U
74#define ITMASK3_REG 0x82U
75#define ITMASK4_REG 0x83U
76#define ITSETMASK1_REG 0x90U
77#define ITSETMASK2_REG 0x91U
78#define ITSETMASK3_REG 0x92U
79#define ITSETMASK4_REG 0x93U
80#define ITCLEARMASK1_REG 0xA0U
81#define ITCLEARMASK2_REG 0xA1U
82#define ITCLEARMASK3_REG 0xA2U
83#define ITCLEARMASK4_REG 0xA3U
84#define ITSOURCE1_REG 0xB0U
85#define ITSOURCE2_REG 0xB1U
86#define ITSOURCE3_REG 0xB2U
87#define ITSOURCE4_REG 0xB3U
88#define LDO_VOLTAGE_MASK 0x7CU
89#define BUCK_VOLTAGE_MASK 0xFCU
90#define LDO_BUCK_VOLTAGE_SHIFT 2
91#define LDO_ENABLE_MASK 0x01U
92#define BUCK_ENABLE_MASK 0x01U
93#define BUCK_HPLP_ENABLE_MASK 0x02U
94#define LDO_HPLP_ENABLE_MASK 0x02U
95#define LDO_BUCK_HPLP_SHIFT 1
96#define LDO_BUCK_RANK_MASK 0x01U
97#define LDO_BUCK_RESET_MASK 0x01U
98#define LDO_BUCK_PULL_DOWN_MASK 0x03U
99
100/* Main PMIC Control Register (MAIN_CONTROL_REG) */
101#define ICC_EVENT_ENABLED BIT(4)
102#define PWRCTRL_POLARITY_HIGH BIT(3)
103#define PWRCTRL_PIN_VALID BIT(2)
104#define RESTART_REQUEST_ENABLED BIT(1)
105#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
106
107/* Main PMIC PADS Control Register (PADS_PULL_REG) */
108#define WAKEUP_DETECTOR_DISABLED BIT(4)
109#define PWRCTRL_PD_ACTIVE BIT(3)
110#define PWRCTRL_PU_ACTIVE BIT(2)
111#define WAKEUP_PD_ACTIVE BIT(1)
112#define PONKEY_PU_ACTIVE BIT(0)
113
114/* Main PMIC VINLOW Control Register (VIN_CONTROL_REGC DMSC) */
115#define SWIN_DETECTOR_ENABLED BIT(7)
116#define SWOUT_DETECTOR_ENABLED BIT(6)
117#define VINLOW_HYST_MASK 0x3
118#define VINLOW_HYST_SHIFT 4
119#define VINLOW_THRESHOLD_MASK 0x7
120#define VINLOW_THRESHOLD_SHIFT 1
121#define VINLOW_ENABLED 0x01
122#define VINLOW_CTRL_REG_MASK 0xFF
123
124/* USB Control Register */
125#define BOOST_OVP_DISABLED BIT(7)
126#define VBUS_OTG_DETECTION_DISABLED BIT(6)
127#define OCP_LIMIT_HIGH BIT(3)
128#define SWIN_SWOUT_ENABLED BIT(2)
129#define USBSW_OTG_SWITCH_ENABLED BIT(1)
130
131int stpmu1_switch_off(void);
132int stpmu1_register_read(uint8_t register_id, uint8_t *value);
133int stpmu1_register_write(uint8_t register_id, uint8_t value);
134int stpmu1_register_update(uint8_t register_id, uint8_t value, uint8_t mask);
135int stpmu1_regulator_enable(const char *name);
136int stpmu1_regulator_disable(const char *name);
137uint8_t stpmu1_is_regulator_enabled(const char *name);
138int stpmu1_regulator_voltage_set(const char *name, uint16_t millivolts);
139void stpmu1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr);
140
141#endif /* __STPMU1_H__ */