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Jacky Baia6177002019-03-06 17:15:06 +08001/*
Jacky Bai0e400552022-03-14 17:14:26 +08002 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved.
Jacky Baia6177002019-03-06 17:15:06 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <stdbool.h>
9
10#include <platform_def.h>
11
12#include <arch_helpers.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
15#include <context.h>
16#include <drivers/arm/tzc380.h>
17#include <drivers/console.h>
18#include <drivers/generic_delay_timer.h>
19#include <lib/el3_runtime/context_mgmt.h>
20#include <lib/mmio.h>
Ji Luoe329b3d2020-02-20 23:47:21 +080021#include <lib/xlat_tables/xlat_tables_v2.h>
Jacky Baia6177002019-03-06 17:15:06 +080022#include <plat/common/platform.h>
23
24#include <gpc.h>
Jacky Bai91c6d322019-05-21 20:24:52 +080025#include <imx_aipstz.h>
Jacky Baia6177002019-03-06 17:15:06 +080026#include <imx_uart.h>
Jacky Bai64130a32019-07-18 13:43:17 +080027#include <imx_rdc.h>
Jacky Bai3bf04a52019-06-12 17:41:47 +080028#include <imx8m_caam.h>
Jacky Bai3c3c2682020-01-07 14:53:54 +080029#include <imx8m_csu.h>
Jacky Baia6177002019-03-06 17:15:06 +080030#include <plat_imx8.h>
31
Ji Luo1c33a2e2020-02-21 10:36:47 +080032#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
33
Jacky Baia6177002019-03-06 17:15:06 +080034static const mmap_region_t imx_mmap[] = {
35 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW),
36 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
37 {0},
38};
39
Jacky Bai91c6d322019-05-21 20:24:52 +080040static const struct aipstz_cfg aipstz[] = {
41 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
42 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
43 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
44 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
45 {0},
46};
47
Jacky Bai64130a32019-07-18 13:43:17 +080048static const struct imx_rdc_cfg rdc[] = {
49 /* Master domain assignment */
Jacky Bai0e400552022-03-14 17:14:26 +080050 RDC_MDAn(RDC_MDA_M4, DID1),
Jacky Bai64130a32019-07-18 13:43:17 +080051
52 /* peripherals domain permission */
Jacky Bai0e400552022-03-14 17:14:26 +080053 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
54 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
Jacky Bai64130a32019-07-18 13:43:17 +080055
56 /* memory region */
57
58 /* Sentinel */
59 {0},
60};
61
Jacky Bai3c3c2682020-01-07 14:53:54 +080062static const struct imx_csu_cfg csu_cfg[] = {
63 /* peripherals csl setting */
64 CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED),
65
66 /* master HP0~1 */
67
68 /* SA setting */
69
70 /* HP control setting */
71
72 /* Sentinel */
73 {0}
74};
75
Jacky Baia6177002019-03-06 17:15:06 +080076static entry_point_info_t bl32_image_ep_info;
77static entry_point_info_t bl33_image_ep_info;
78
79/* get SPSR for BL33 entry */
80static uint32_t get_spsr_for_bl33_entry(void)
81{
82 unsigned long el_status;
83 unsigned long mode;
84 uint32_t spsr;
85
86 /* figure out what mode we enter the non-secure world */
87 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
88 el_status &= ID_AA64PFR0_ELX_MASK;
89
90 mode = (el_status) ? MODE_EL2 : MODE_EL1;
91
92 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
93 return spsr;
94}
95
96void bl31_tzc380_setup(void)
97{
98 unsigned int val;
99
100 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
101 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
102 return;
103
104 tzc380_init(IMX_TZASC_BASE);
105
106 /*
107 * Need to substact offset 0x40000000 from CPU address when
108 * programming tzasc region for i.mx8mm.
109 */
110
111 /* Enable 1G-5G S/NS RW */
112 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
113 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
114}
115
116void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
117 u_register_t arg2, u_register_t arg3)
118{
Andre Przywara7110d992020-01-25 00:58:35 +0000119 static console_t console;
Jacky Baia6177002019-03-06 17:15:06 +0800120 int i;
121
122 /* Enable CSU NS access permission */
123 for (i = 0; i < 64; i++) {
124 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
125 }
126
Jacky Bai91c6d322019-05-21 20:24:52 +0800127 imx_aipstz_init(aipstz);
Jacky Baia6177002019-03-06 17:15:06 +0800128
Jacky Bai64130a32019-07-18 13:43:17 +0800129 imx_rdc_init(rdc);
130
Jacky Bai3c3c2682020-01-07 14:53:54 +0800131 imx_csu_init(csu_cfg);
132
Jacky Bai3bf04a52019-06-12 17:41:47 +0800133 imx8m_caam_init();
134
Jacky Baia6177002019-03-06 17:15:06 +0800135 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
136 IMX_CONSOLE_BAUDRATE, &console);
137 /* This console is only used for boot stage */
Andre Przywara7110d992020-01-25 00:58:35 +0000138 console_set_scope(&console, CONSOLE_FLAG_BOOT);
Jacky Baia6177002019-03-06 17:15:06 +0800139
140 /*
141 * tell BL3-1 where the non-secure software image is located
142 * and the entry state information.
143 */
144 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
145 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
146 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
147
Ji Luo1c33a2e2020-02-21 10:36:47 +0800148#if defined(SPD_opteed) || defined(SPD_trusty)
Jacky Bai2a763ba2019-07-18 13:34:09 +0800149 /* Populate entry point information for BL32 */
150 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
151 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
152 bl32_image_ep_info.pc = BL32_BASE;
153 bl32_image_ep_info.spsr = 0;
154
Silvano di Ninnob723a552020-03-25 09:24:51 +0100155 /* Pass TEE base and size to bl33 */
156 bl33_image_ep_info.args.arg1 = BL32_BASE;
157 bl33_image_ep_info.args.arg2 = BL32_SIZE;
158
Ji Luo1c33a2e2020-02-21 10:36:47 +0800159#ifdef SPD_trusty
160 bl32_image_ep_info.args.arg0 = BL32_SIZE;
161 bl32_image_ep_info.args.arg1 = BL32_BASE;
Silvano di Ninnob723a552020-03-25 09:24:51 +0100162#else
163 /* Make sure memory is clean */
164 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
165 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
166 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
Ji Luo1c33a2e2020-02-21 10:36:47 +0800167#endif
Jacky Bai2a763ba2019-07-18 13:34:09 +0800168#endif
169
Jacky Baia6177002019-03-06 17:15:06 +0800170 bl31_tzc380_setup();
171}
172
173void bl31_plat_arch_setup(void)
174{
175 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
176 MT_MEMORY | MT_RW | MT_SECURE);
177 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
178 MT_MEMORY | MT_RO | MT_SECURE);
179#if USE_COHERENT_MEM
180 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
181 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE),
182 MT_DEVICE | MT_RW | MT_SECURE);
183#endif
Ji Luo1c33a2e2020-02-21 10:36:47 +0800184 /* Map TEE memory */
185 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW);
186
Jacky Baia6177002019-03-06 17:15:06 +0800187 mmap_add(imx_mmap);
188
189 init_xlat_tables();
190
191 enable_mmu_el3(0);
192}
193
194void bl31_platform_setup(void)
195{
196 generic_delay_timer_init();
197
198 /* select the CKIL source to 32K OSC */
199 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
200
201 plat_gic_driver_init();
202 plat_gic_init();
203
204 imx_gpc_init();
205}
206
207entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
208{
209 if (type == NON_SECURE)
210 return &bl33_image_ep_info;
211 if (type == SECURE)
212 return &bl32_image_ep_info;
213
214 return NULL;
215}
216
217unsigned int plat_get_syscnt_freq2(void)
218{
219 return COUNTER_FREQUENCY;
220}
Ji Luo1c33a2e2020-02-21 10:36:47 +0800221
222#ifdef SPD_trusty
223void plat_trusty_set_boot_args(aapcs64_params_t *args)
224{
225 args->arg0 = BL32_SIZE;
226 args->arg1 = BL32_BASE;
227 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
228}
229#endif