Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 1 | /* |
Jacky Bai | 0e40055 | 2022-03-14 17:14:26 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved. |
Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | #include <stdbool.h> |
| 9 | |
| 10 | #include <platform_def.h> |
| 11 | |
| 12 | #include <arch_helpers.h> |
| 13 | #include <common/bl_common.h> |
| 14 | #include <common/debug.h> |
| 15 | #include <context.h> |
| 16 | #include <drivers/arm/tzc380.h> |
| 17 | #include <drivers/console.h> |
| 18 | #include <drivers/generic_delay_timer.h> |
| 19 | #include <lib/el3_runtime/context_mgmt.h> |
| 20 | #include <lib/mmio.h> |
Ji Luo | e329b3d | 2020-02-20 23:47:21 +0800 | [diff] [blame^] | 21 | #include <lib/xlat_tables/xlat_tables_v2.h> |
Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 22 | #include <plat/common/platform.h> |
| 23 | |
| 24 | #include <gpc.h> |
Jacky Bai | 91c6d32 | 2019-05-21 20:24:52 +0800 | [diff] [blame] | 25 | #include <imx_aipstz.h> |
Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 26 | #include <imx_uart.h> |
Jacky Bai | 64130a3 | 2019-07-18 13:43:17 +0800 | [diff] [blame] | 27 | #include <imx_rdc.h> |
Jacky Bai | 3bf04a5 | 2019-06-12 17:41:47 +0800 | [diff] [blame] | 28 | #include <imx8m_caam.h> |
Jacky Bai | 3c3c268 | 2020-01-07 14:53:54 +0800 | [diff] [blame] | 29 | #include <imx8m_csu.h> |
Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 30 | #include <plat_imx8.h> |
| 31 | |
| 32 | static const mmap_region_t imx_mmap[] = { |
| 33 | MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), |
| 34 | MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ |
| 35 | {0}, |
| 36 | }; |
| 37 | |
Jacky Bai | 91c6d32 | 2019-05-21 20:24:52 +0800 | [diff] [blame] | 38 | static const struct aipstz_cfg aipstz[] = { |
| 39 | {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, |
| 40 | {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, |
| 41 | {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, |
| 42 | {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, |
| 43 | {0}, |
| 44 | }; |
| 45 | |
Jacky Bai | 64130a3 | 2019-07-18 13:43:17 +0800 | [diff] [blame] | 46 | static const struct imx_rdc_cfg rdc[] = { |
| 47 | /* Master domain assignment */ |
Jacky Bai | 0e40055 | 2022-03-14 17:14:26 +0800 | [diff] [blame] | 48 | RDC_MDAn(RDC_MDA_M4, DID1), |
Jacky Bai | 64130a3 | 2019-07-18 13:43:17 +0800 | [diff] [blame] | 49 | |
| 50 | /* peripherals domain permission */ |
Jacky Bai | 0e40055 | 2022-03-14 17:14:26 +0800 | [diff] [blame] | 51 | RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), |
| 52 | RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), |
Jacky Bai | 64130a3 | 2019-07-18 13:43:17 +0800 | [diff] [blame] | 53 | |
| 54 | /* memory region */ |
| 55 | |
| 56 | /* Sentinel */ |
| 57 | {0}, |
| 58 | }; |
| 59 | |
Jacky Bai | 3c3c268 | 2020-01-07 14:53:54 +0800 | [diff] [blame] | 60 | static const struct imx_csu_cfg csu_cfg[] = { |
| 61 | /* peripherals csl setting */ |
| 62 | CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED), |
| 63 | |
| 64 | /* master HP0~1 */ |
| 65 | |
| 66 | /* SA setting */ |
| 67 | |
| 68 | /* HP control setting */ |
| 69 | |
| 70 | /* Sentinel */ |
| 71 | {0} |
| 72 | }; |
| 73 | |
Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 74 | static entry_point_info_t bl32_image_ep_info; |
| 75 | static entry_point_info_t bl33_image_ep_info; |
| 76 | |
| 77 | /* get SPSR for BL33 entry */ |
| 78 | static uint32_t get_spsr_for_bl33_entry(void) |
| 79 | { |
| 80 | unsigned long el_status; |
| 81 | unsigned long mode; |
| 82 | uint32_t spsr; |
| 83 | |
| 84 | /* figure out what mode we enter the non-secure world */ |
| 85 | el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; |
| 86 | el_status &= ID_AA64PFR0_ELX_MASK; |
| 87 | |
| 88 | mode = (el_status) ? MODE_EL2 : MODE_EL1; |
| 89 | |
| 90 | spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
| 91 | return spsr; |
| 92 | } |
| 93 | |
| 94 | void bl31_tzc380_setup(void) |
| 95 | { |
| 96 | unsigned int val; |
| 97 | |
| 98 | val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); |
| 99 | if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) |
| 100 | return; |
| 101 | |
| 102 | tzc380_init(IMX_TZASC_BASE); |
| 103 | |
| 104 | /* |
| 105 | * Need to substact offset 0x40000000 from CPU address when |
| 106 | * programming tzasc region for i.mx8mm. |
| 107 | */ |
| 108 | |
| 109 | /* Enable 1G-5G S/NS RW */ |
| 110 | tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | |
| 111 | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); |
| 112 | } |
| 113 | |
| 114 | void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, |
| 115 | u_register_t arg2, u_register_t arg3) |
| 116 | { |
Andre Przywara | 7110d99 | 2020-01-25 00:58:35 +0000 | [diff] [blame] | 117 | static console_t console; |
Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 118 | int i; |
| 119 | |
| 120 | /* Enable CSU NS access permission */ |
| 121 | for (i = 0; i < 64; i++) { |
| 122 | mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); |
| 123 | } |
| 124 | |
Jacky Bai | 91c6d32 | 2019-05-21 20:24:52 +0800 | [diff] [blame] | 125 | imx_aipstz_init(aipstz); |
Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 126 | |
Jacky Bai | 64130a3 | 2019-07-18 13:43:17 +0800 | [diff] [blame] | 127 | imx_rdc_init(rdc); |
| 128 | |
Jacky Bai | 3c3c268 | 2020-01-07 14:53:54 +0800 | [diff] [blame] | 129 | imx_csu_init(csu_cfg); |
| 130 | |
Jacky Bai | 3bf04a5 | 2019-06-12 17:41:47 +0800 | [diff] [blame] | 131 | imx8m_caam_init(); |
| 132 | |
Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 133 | console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, |
| 134 | IMX_CONSOLE_BAUDRATE, &console); |
| 135 | /* This console is only used for boot stage */ |
Andre Przywara | 7110d99 | 2020-01-25 00:58:35 +0000 | [diff] [blame] | 136 | console_set_scope(&console, CONSOLE_FLAG_BOOT); |
Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 137 | |
| 138 | /* |
| 139 | * tell BL3-1 where the non-secure software image is located |
| 140 | * and the entry state information. |
| 141 | */ |
| 142 | bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; |
| 143 | bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); |
| 144 | SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
| 145 | |
Jacky Bai | 2a763ba | 2019-07-18 13:34:09 +0800 | [diff] [blame] | 146 | #ifdef SPD_opteed |
| 147 | /* Populate entry point information for BL32 */ |
| 148 | SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); |
| 149 | SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); |
| 150 | bl32_image_ep_info.pc = BL32_BASE; |
| 151 | bl32_image_ep_info.spsr = 0; |
| 152 | |
| 153 | /* Pass TEE base and size to bl33 */ |
| 154 | bl33_image_ep_info.args.arg1 = BL32_BASE; |
| 155 | bl33_image_ep_info.args.arg2 = BL32_SIZE; |
| 156 | #endif |
| 157 | |
Jacky Bai | a617700 | 2019-03-06 17:15:06 +0800 | [diff] [blame] | 158 | bl31_tzc380_setup(); |
| 159 | } |
| 160 | |
| 161 | void bl31_plat_arch_setup(void) |
| 162 | { |
| 163 | mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), |
| 164 | MT_MEMORY | MT_RW | MT_SECURE); |
| 165 | mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), |
| 166 | MT_MEMORY | MT_RO | MT_SECURE); |
| 167 | #if USE_COHERENT_MEM |
| 168 | mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, |
| 169 | (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), |
| 170 | MT_DEVICE | MT_RW | MT_SECURE); |
| 171 | #endif |
| 172 | mmap_add(imx_mmap); |
| 173 | |
| 174 | init_xlat_tables(); |
| 175 | |
| 176 | enable_mmu_el3(0); |
| 177 | } |
| 178 | |
| 179 | void bl31_platform_setup(void) |
| 180 | { |
| 181 | generic_delay_timer_init(); |
| 182 | |
| 183 | /* select the CKIL source to 32K OSC */ |
| 184 | mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); |
| 185 | |
| 186 | plat_gic_driver_init(); |
| 187 | plat_gic_init(); |
| 188 | |
| 189 | imx_gpc_init(); |
| 190 | } |
| 191 | |
| 192 | entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) |
| 193 | { |
| 194 | if (type == NON_SECURE) |
| 195 | return &bl33_image_ep_info; |
| 196 | if (type == SECURE) |
| 197 | return &bl32_image_ep_info; |
| 198 | |
| 199 | return NULL; |
| 200 | } |
| 201 | |
| 202 | unsigned int plat_get_syscnt_freq2(void) |
| 203 | { |
| 204 | return COUNTER_FREQUENCY; |
| 205 | } |