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Yann Gautiera3f46382023-06-14 10:40:59 +02001/*
Yann Gautier06ae3962023-09-19 18:26:16 +02002 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
Yann Gautiera3f46382023-06-14 10:40:59 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP2_DEF_H
8#define STM32MP2_DEF_H
9
10#include <common/tbbr/tbbr_img_def.h>
11#ifndef __ASSEMBLER__
12#include <drivers/st/bsec.h>
13#endif
Yann Gautiereb91af52023-06-14 18:05:47 +020014#include <drivers/st/stm32mp25_rcc.h>
Yann Gautier8053f2b2024-05-21 11:46:59 +020015#ifndef __ASSEMBLER__
16#include <drivers/st/stm32mp2_clk.h>
17#endif
18#include <drivers/st/stm32mp2_pwr.h>
Yann Gautiera3f46382023-06-14 10:40:59 +020019#include <dt-bindings/clock/stm32mp25-clks.h>
20#include <dt-bindings/clock/stm32mp25-clksrc.h>
Pascal Paillete521d7d2022-03-16 17:25:57 +010021#include <dt-bindings/gpio/stm32-gpio.h>
Yann Gautiera3f46382023-06-14 10:40:59 +020022#include <dt-bindings/reset/stm32mp25-resets.h>
23
24#ifndef __ASSEMBLER__
25#include <boot_api.h>
Yann Gautier06ae3962023-09-19 18:26:16 +020026#include <stm32mp2_private.h>
Yann Gautiera3f46382023-06-14 10:40:59 +020027#include <stm32mp_common.h>
28#include <stm32mp_dt.h>
29#include <stm32mp_shared_resources.h>
30#endif
31
32/*******************************************************************************
Yann Gautier400dcac2024-06-21 14:49:47 +020033 * CHIP ID
34 ******************************************************************************/
35#define STM32MP2_CHIP_ID U(0x505)
36
37#define STM32MP251A_PART_NB U(0x400B3E6D)
38#define STM32MP251C_PART_NB U(0x000B306D)
39#define STM32MP251D_PART_NB U(0xC00B3E6D)
40#define STM32MP251F_PART_NB U(0x800B306D)
41#define STM32MP253A_PART_NB U(0x400B3E0C)
42#define STM32MP253C_PART_NB U(0x000B300C)
43#define STM32MP253D_PART_NB U(0xC00B3E0C)
44#define STM32MP253F_PART_NB U(0x800B300C)
45#define STM32MP255A_PART_NB U(0x40082E00)
46#define STM32MP255C_PART_NB U(0x00082000)
47#define STM32MP255D_PART_NB U(0xC0082E00)
48#define STM32MP255F_PART_NB U(0x80082000)
49#define STM32MP257A_PART_NB U(0x40002E00)
50#define STM32MP257C_PART_NB U(0x00002000)
51#define STM32MP257D_PART_NB U(0xC0002E00)
52#define STM32MP257F_PART_NB U(0x80002000)
53
54#define STM32MP2_REV_A U(0x08)
55#define STM32MP2_REV_B U(0x10)
56#define STM32MP2_REV_X U(0x12)
57#define STM32MP2_REV_Y U(0x11)
58#define STM32MP2_REV_Z U(0x09)
59
60/*******************************************************************************
61 * PACKAGE ID
62 ******************************************************************************/
63#define STM32MP25_PKG_CUSTOM U(0)
64#define STM32MP25_PKG_AL_VFBGA361 U(1)
65#define STM32MP25_PKG_AK_VFBGA424 U(3)
66#define STM32MP25_PKG_AI_TFBGA436 U(5)
67#define STM32MP25_PKG_UNKNOWN U(7)
68
69/*******************************************************************************
Yann Gautiera3f46382023-06-14 10:40:59 +020070 * STM32MP2 memory map related constants
71 ******************************************************************************/
72#define STM32MP_SYSRAM_BASE U(0x0E000000)
73#define STM32MP_SYSRAM_SIZE U(0x00040000)
Maxime Méréb151f682024-09-13 17:57:58 +020074#define SRAM1_BASE U(0x0E040000)
75#define SRAM1_SIZE_FOR_TFA U(0x00010000)
Yann Gautierece4c252023-06-13 18:45:03 +020076#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
Yann Gautiera3f46382023-06-14 10:40:59 +020077
Yann Gautiera3f46382023-06-14 10:40:59 +020078/* DDR configuration */
79#define STM32MP_DDR_BASE U(0x80000000)
80#define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
81
82/* DDR power initializations */
83#ifndef __ASSEMBLER__
84enum ddr_type {
85 STM32MP_DDR3,
86 STM32MP_DDR4,
87 STM32MP_LPDDR4
88};
89#endif
90
Yann Gautier626ec9d2023-06-14 18:44:41 +020091/* Section used inside TF binaries */
92#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
Yann Gautier8053f2b2024-05-21 11:46:59 +020093/* 512 Bytes reserved for header */
Yann Gautier626ec9d2023-06-14 18:44:41 +020094#define STM32MP_HEADER_SIZE U(0x00000200)
Yann Gautier8053f2b2024-05-21 11:46:59 +020095#define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \
Yann Gautier626ec9d2023-06-14 18:44:41 +020096 STM32MP_PARAM_LOAD_SIZE)
97
98/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
99#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
100
Yann Gautier8053f2b2024-05-21 11:46:59 +0200101#define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \
Yann Gautier626ec9d2023-06-14 18:44:41 +0200102 STM32MP_PARAM_LOAD_SIZE + \
103 STM32MP_HEADER_SIZE)
104
Yann Gautier8053f2b2024-05-21 11:46:59 +0200105#define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \
Yann Gautier626ec9d2023-06-14 18:44:41 +0200106 (STM32MP_PARAM_LOAD_SIZE + \
107 STM32MP_HEADER_SIZE))
108
Yann Gautier8053f2b2024-05-21 11:46:59 +0200109#define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */
110#define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
Yann Gautiera3f46382023-06-14 10:40:59 +0200111
Maxime Méréb95a3752024-09-20 17:16:20 +0200112/* Allocate remaining sysram to BL31 Binary only */
Yann Gautierece4c252023-06-13 18:45:03 +0200113#define STM32MP_BL31_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
114 STM32MP_BL2_SIZE)
115
Maxime Méréb95a3752024-09-20 17:16:20 +0200116#define BL31_PROGBITS_LIMIT STM32MP_BL31_SIZE
117
Yann Gautier8053f2b2024-05-21 11:46:59 +0200118#define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \
119 STM32MP_SYSRAM_SIZE - \
Yann Gautiera3f46382023-06-14 10:40:59 +0200120 STM32MP_BL2_SIZE)
121
Yann Gautier8053f2b2024-05-21 11:46:59 +0200122#define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE
123
124#define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
125 STM32MP_BL2_RO_SIZE)
126
127#define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \
128 STM32MP_SYSRAM_SIZE - \
129 STM32MP_BL2_RW_BASE)
130
Yann Gautiera3f46382023-06-14 10:40:59 +0200131/* BL2 and BL32/sp_min require 4 tables */
132#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
133
134/*
135 * MAX_MMAP_REGIONS is usually:
136 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
137 */
138#define MAX_MMAP_REGIONS 6
139
Yann Gautier626ec9d2023-06-14 18:44:41 +0200140/* DTB initialization value */
Yann Gautier8053f2b2024-05-21 11:46:59 +0200141#define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
Yann Gautier626ec9d2023-06-14 18:44:41 +0200142
143#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
144 STM32MP_BL2_DTB_SIZE)
145
Yann Gautier8053f2b2024-05-21 11:46:59 +0200146#if defined(IMAGE_BL2)
147#define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
148#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
149#endif
150
Maxime Méréb151f682024-09-13 17:57:58 +0200151#if STM32MP_DDR_FIP_IO_STORAGE
152#define STM32MP_DDR_FW_BASE SRAM1_BASE
153#define STM32MP_DDR_FW_MAX_SIZE U(0x8800)
154#endif
155
Yann Gautier99f41322024-05-22 16:16:59 +0200156#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE
157#define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE
158
Yann Gautiera3f46382023-06-14 10:40:59 +0200159#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
160#define STM32MP_BL33_MAX_SIZE U(0x400000)
Yann Gautier99f41322024-05-22 16:16:59 +0200161#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
162 STM32MP_BL33_MAX_SIZE)
163#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000)
Yann Gautiera3f46382023-06-14 10:40:59 +0200164
165/*******************************************************************************
Yann Gautier8053f2b2024-05-21 11:46:59 +0200166 * STM32MP2 device/io map related constants (used for MMU)
167 ******************************************************************************/
168#define STM32MP_DEVICE_BASE U(0x40000000)
169#define STM32MP_DEVICE_SIZE U(0x40000000)
170
171/*******************************************************************************
Yann Gautiera3f46382023-06-14 10:40:59 +0200172 * STM32MP2 RCC
173 ******************************************************************************/
174#define RCC_BASE U(0x44200000)
175
176/*******************************************************************************
177 * STM32MP2 PWR
178 ******************************************************************************/
179#define PWR_BASE U(0x44210000)
180
181/*******************************************************************************
Yann Gautiereb91af52023-06-14 18:05:47 +0200182 * STM32MP2 GPIO
183 ******************************************************************************/
184#define GPIOA_BASE U(0x44240000)
185#define GPIOB_BASE U(0x44250000)
186#define GPIOC_BASE U(0x44260000)
187#define GPIOD_BASE U(0x44270000)
188#define GPIOE_BASE U(0x44280000)
189#define GPIOF_BASE U(0x44290000)
190#define GPIOG_BASE U(0x442A0000)
191#define GPIOH_BASE U(0x442B0000)
192#define GPIOI_BASE U(0x442C0000)
193#define GPIOJ_BASE U(0x442D0000)
194#define GPIOK_BASE U(0x442E0000)
195#define GPIOZ_BASE U(0x46200000)
196#define GPIO_BANK_OFFSET U(0x10000)
197
198#define STM32MP_GPIOS_PIN_MAX_COUNT 16
199#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
200
201/*******************************************************************************
202 * STM32MP2 UART
203 ******************************************************************************/
204#define USART1_BASE U(0x40330000)
205#define USART2_BASE U(0x400E0000)
206#define USART3_BASE U(0x400F0000)
207#define UART4_BASE U(0x40100000)
208#define UART5_BASE U(0x40110000)
209#define USART6_BASE U(0x40220000)
210#define UART7_BASE U(0x40370000)
211#define UART8_BASE U(0x40380000)
212#define UART9_BASE U(0x402C0000)
213#define STM32MP_NB_OF_UART U(9)
214
215/* For UART crash console */
216#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
217/* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
218#define STM32MP_DEBUG_USART_BASE USART2_BASE
219#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
220#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
221#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
222#define DEBUG_UART_TX_GPIO_PORT 4
223#define DEBUG_UART_TX_GPIO_ALTERNATE 6
224#define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
225#define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
226#define DEBUG_UART_TX_EN_REG RCC_USART2CFGR
227#define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
228#define DEBUG_UART_RST_REG RCC_USART2CFGR
229#define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
230#define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
231#define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
232
233/*******************************************************************************
Yann Gautiera3f46382023-06-14 10:40:59 +0200234 * STM32MP2 SDMMC
235 ******************************************************************************/
236#define STM32MP_SDMMC1_BASE U(0x48220000)
237#define STM32MP_SDMMC2_BASE U(0x48230000)
238#define STM32MP_SDMMC3_BASE U(0x48240000)
239
240/*******************************************************************************
Yann Gautiera585d762024-01-03 14:28:23 +0100241 * STM32MP2 BSEC / OTP
242 ******************************************************************************/
243/*
244 * 367 available OTPs, the other are masked
245 * - ECIES key: 368 to 375 (only readable by bootrom)
246 * - HWKEY: 376 to 383 (never reloadable or readable)
247 */
248#define STM32MP2_OTP_MAX_ID U(0x16F)
249#define STM32MP2_MID_OTP_START U(0x80)
250#define STM32MP2_UPPER_OTP_START U(0x100)
251
252/* OTP labels */
253#define PART_NUMBER_OTP "part-number-otp"
Yann Gautier400dcac2024-06-21 14:49:47 +0200254#define REVISION_OTP "rev_otp"
Yann Gautiera585d762024-01-03 14:28:23 +0100255#define PACKAGE_OTP "package-otp"
256#define HCONF1_OTP "otp124"
257#define NAND_OTP "otp16"
258#define NAND2_OTP "otp20"
259#define BOARD_ID_OTP "board-id"
260#define UID_OTP "uid-otp"
261#define LIFECYCLE2_OTP "otp18"
262#define PKH_OTP "otp144"
263#define ENCKEY_OTP "otp260"
264
265/* OTP mask */
266/* PACKAGE */
267#define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0)
268#define PACKAGE_OTP_PKG_SHIFT U(0)
269
270/* IWDG OTP */
271#define HCONF1_OTP_IWDG_HW_POS U(0)
272#define HCONF1_OTP_IWDG_FZ_STOP_POS U(1)
273#define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2)
274
275/* NAND OTP */
276/* NAND parameter storage flag */
277#define NAND_PARAM_STORED_IN_OTP BIT_32(31)
278
279/* NAND page size in bytes */
280#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
281#define NAND_PAGE_SIZE_SHIFT U(29)
282#define NAND_PAGE_SIZE_2K U(0)
283#define NAND_PAGE_SIZE_4K U(1)
284#define NAND_PAGE_SIZE_8K U(2)
285
286/* NAND block size in pages */
287#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
288#define NAND_BLOCK_SIZE_SHIFT U(27)
289#define NAND_BLOCK_SIZE_64_PAGES U(0)
290#define NAND_BLOCK_SIZE_128_PAGES U(1)
291#define NAND_BLOCK_SIZE_256_PAGES U(2)
292
293/* NAND number of block (in unit of 256 blocks) */
294#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
295#define NAND_BLOCK_NB_SHIFT U(19)
296#define NAND_BLOCK_NB_UNIT U(256)
297
298/* NAND bus width in bits */
299#define NAND_WIDTH_MASK BIT_32(18)
300#define NAND_WIDTH_SHIFT U(18)
301
302/* NAND number of ECC bits per 512 bytes */
303#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
304#define NAND_ECC_BIT_NB_SHIFT U(15)
305#define NAND_ECC_BIT_NB_UNSET U(0)
306#define NAND_ECC_BIT_NB_1_BITS U(1)
307#define NAND_ECC_BIT_NB_4_BITS U(2)
308#define NAND_ECC_BIT_NB_8_BITS U(3)
309#define NAND_ECC_ON_DIE U(4)
310
311/* NAND number of planes */
312#define NAND_PLANE_BIT_NB_MASK BIT_32(14)
313
314/* NAND2 OTP */
315#define NAND2_PAGE_SIZE_SHIFT U(16)
316
317/* NAND2 config distribution */
318#define NAND2_CONFIG_DISTRIB BIT_32(0)
319#define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
320#define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
321
322/* MONOTONIC OTP */
323#define MAX_MONOTONIC_VALUE U(32)
324
325/* UID OTP */
326#define UID_WORD_NB U(3)
327
328/* Lifecycle OTP */
329#define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0)
330
331/*******************************************************************************
Yann Gautiera3f46382023-06-14 10:40:59 +0200332 * STM32MP2 TAMP
333 ******************************************************************************/
334#define PLAT_MAX_TAMP_INT U(5)
335#define PLAT_MAX_TAMP_EXT U(3)
336#define TAMP_BASE U(0x46010000)
337#define TAMP_SMCR (TAMP_BASE + U(0x20))
338#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
339#define TAMP_BKP_REG_CLK CK_BUS_RTC
340#define TAMP_BKP_SEC_NUMBER U(10)
341#define TAMP_COUNTR U(0x40)
342
343#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
344static inline uintptr_t tamp_bkpr(uint32_t idx)
345{
346 return TAMP_BKP_REGISTER_BASE + (idx << 2);
347}
348#endif
349
350/*******************************************************************************
351 * STM32MP2 DDRCTRL
352 ******************************************************************************/
353#define DDRCTRL_BASE U(0x48040000)
354
355/*******************************************************************************
356 * STM32MP2 DDRDBG
357 ******************************************************************************/
358#define DDRDBG_BASE U(0x48050000)
359
360/*******************************************************************************
361 * STM32MP2 DDRPHYC
362 ******************************************************************************/
363#define DDRPHYC_BASE U(0x48C00000)
364
365/*******************************************************************************
366 * Miscellaneous STM32MP1 peripherals base address
367 ******************************************************************************/
368#define BSEC_BASE U(0x44000000)
369#define DBGMCU_BASE U(0x4A010000)
370#define HASH_BASE U(0x42010000)
371#define RTC_BASE U(0x46000000)
372#define STGEN_BASE U(0x48080000)
373#define SYSCFG_BASE U(0x44230000)
374
375/*******************************************************************************
Maxime Méréb151f682024-09-13 17:57:58 +0200376 * STM32MP RIF
377 ******************************************************************************/
378#define RISAB3_BASE U(0x42110000)
379
380/*******************************************************************************
Gabriel Fernandezbcd95062022-04-20 10:08:49 +0200381 * STM32MP CA35SSC
382 ******************************************************************************/
383#define A35SSC_BASE U(0x48800000)
384
385/*******************************************************************************
Yann Gautiera3f46382023-06-14 10:40:59 +0200386 * REGULATORS
387 ******************************************************************************/
388/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
389#define PLAT_NB_RDEVS U(19)
390/* 2 FIXED */
391#define PLAT_NB_FIXED_REGUS U(2)
392/* No GPIO regu */
393#define PLAT_NB_GPIO_REGUS U(0)
394
395/*******************************************************************************
396 * Device Tree defines
397 ******************************************************************************/
398#define DT_BSEC_COMPAT "st,stm32mp25-bsec"
399#define DT_DDR_COMPAT "st,stm32mp2-ddr"
400#define DT_PWR_COMPAT "st,stm32mp25-pwr"
401#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
Yann Gautier8053f2b2024-05-21 11:46:59 +0200402#define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2"
Yann Gautiera3f46382023-06-14 10:40:59 +0200403#define DT_UART_COMPAT "st,stm32h7-uart"
404
405#endif /* STM32MP2_DEF_H */