Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2023, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef STM32MP2_DEF_H |
| 8 | #define STM32MP2_DEF_H |
| 9 | |
| 10 | #include <common/tbbr/tbbr_img_def.h> |
| 11 | #ifndef __ASSEMBLER__ |
| 12 | #include <drivers/st/bsec.h> |
| 13 | #endif |
| 14 | #include <dt-bindings/clock/stm32mp25-clks.h> |
| 15 | #include <dt-bindings/clock/stm32mp25-clksrc.h> |
| 16 | #include <dt-bindings/reset/stm32mp25-resets.h> |
| 17 | |
| 18 | #ifndef __ASSEMBLER__ |
| 19 | #include <boot_api.h> |
| 20 | #include <stm32mp_common.h> |
| 21 | #include <stm32mp_dt.h> |
| 22 | #include <stm32mp_shared_resources.h> |
| 23 | #endif |
| 24 | |
| 25 | /******************************************************************************* |
| 26 | * STM32MP2 memory map related constants |
| 27 | ******************************************************************************/ |
| 28 | #define STM32MP_SYSRAM_BASE U(0x0E000000) |
| 29 | #define STM32MP_SYSRAM_SIZE U(0x00040000) |
| 30 | |
| 31 | #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE |
| 32 | #define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE |
| 33 | |
| 34 | /* DDR configuration */ |
| 35 | #define STM32MP_DDR_BASE U(0x80000000) |
| 36 | #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ |
| 37 | |
| 38 | /* DDR power initializations */ |
| 39 | #ifndef __ASSEMBLER__ |
| 40 | enum ddr_type { |
| 41 | STM32MP_DDR3, |
| 42 | STM32MP_DDR4, |
| 43 | STM32MP_LPDDR4 |
| 44 | }; |
| 45 | #endif |
| 46 | |
| 47 | #define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */ |
| 48 | |
| 49 | #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ |
| 50 | STM32MP_SEC_SYSRAM_SIZE - \ |
| 51 | STM32MP_BL2_SIZE) |
| 52 | |
| 53 | /* BL2 and BL32/sp_min require 4 tables */ |
| 54 | #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ |
| 55 | |
| 56 | /* |
| 57 | * MAX_MMAP_REGIONS is usually: |
| 58 | * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup |
| 59 | */ |
| 60 | #define MAX_MMAP_REGIONS 6 |
| 61 | |
| 62 | #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) |
| 63 | #define STM32MP_BL33_MAX_SIZE U(0x400000) |
| 64 | |
| 65 | /******************************************************************************* |
| 66 | * STM32MP2 RCC |
| 67 | ******************************************************************************/ |
| 68 | #define RCC_BASE U(0x44200000) |
| 69 | |
| 70 | /******************************************************************************* |
| 71 | * STM32MP2 PWR |
| 72 | ******************************************************************************/ |
| 73 | #define PWR_BASE U(0x44210000) |
| 74 | |
| 75 | /******************************************************************************* |
| 76 | * STM32MP2 SDMMC |
| 77 | ******************************************************************************/ |
| 78 | #define STM32MP_SDMMC1_BASE U(0x48220000) |
| 79 | #define STM32MP_SDMMC2_BASE U(0x48230000) |
| 80 | #define STM32MP_SDMMC3_BASE U(0x48240000) |
| 81 | |
| 82 | /******************************************************************************* |
| 83 | * STM32MP2 TAMP |
| 84 | ******************************************************************************/ |
| 85 | #define PLAT_MAX_TAMP_INT U(5) |
| 86 | #define PLAT_MAX_TAMP_EXT U(3) |
| 87 | #define TAMP_BASE U(0x46010000) |
| 88 | #define TAMP_SMCR (TAMP_BASE + U(0x20)) |
| 89 | #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) |
| 90 | #define TAMP_BKP_REG_CLK CK_BUS_RTC |
| 91 | #define TAMP_BKP_SEC_NUMBER U(10) |
| 92 | #define TAMP_COUNTR U(0x40) |
| 93 | |
| 94 | #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) |
| 95 | static inline uintptr_t tamp_bkpr(uint32_t idx) |
| 96 | { |
| 97 | return TAMP_BKP_REGISTER_BASE + (idx << 2); |
| 98 | } |
| 99 | #endif |
| 100 | |
| 101 | /******************************************************************************* |
| 102 | * STM32MP2 DDRCTRL |
| 103 | ******************************************************************************/ |
| 104 | #define DDRCTRL_BASE U(0x48040000) |
| 105 | |
| 106 | /******************************************************************************* |
| 107 | * STM32MP2 DDRDBG |
| 108 | ******************************************************************************/ |
| 109 | #define DDRDBG_BASE U(0x48050000) |
| 110 | |
| 111 | /******************************************************************************* |
| 112 | * STM32MP2 DDRPHYC |
| 113 | ******************************************************************************/ |
| 114 | #define DDRPHYC_BASE U(0x48C00000) |
| 115 | |
| 116 | /******************************************************************************* |
| 117 | * Miscellaneous STM32MP1 peripherals base address |
| 118 | ******************************************************************************/ |
| 119 | #define BSEC_BASE U(0x44000000) |
| 120 | #define DBGMCU_BASE U(0x4A010000) |
| 121 | #define HASH_BASE U(0x42010000) |
| 122 | #define RTC_BASE U(0x46000000) |
| 123 | #define STGEN_BASE U(0x48080000) |
| 124 | #define SYSCFG_BASE U(0x44230000) |
| 125 | |
| 126 | /******************************************************************************* |
| 127 | * REGULATORS |
| 128 | ******************************************************************************/ |
| 129 | /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ |
| 130 | #define PLAT_NB_RDEVS U(19) |
| 131 | /* 2 FIXED */ |
| 132 | #define PLAT_NB_FIXED_REGUS U(2) |
| 133 | /* No GPIO regu */ |
| 134 | #define PLAT_NB_GPIO_REGUS U(0) |
| 135 | |
| 136 | /******************************************************************************* |
| 137 | * Device Tree defines |
| 138 | ******************************************************************************/ |
| 139 | #define DT_BSEC_COMPAT "st,stm32mp25-bsec" |
| 140 | #define DT_DDR_COMPAT "st,stm32mp2-ddr" |
| 141 | #define DT_PWR_COMPAT "st,stm32mp25-pwr" |
| 142 | #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" |
| 143 | #define DT_UART_COMPAT "st,stm32h7-uart" |
| 144 | |
| 145 | #endif /* STM32MP2_DEF_H */ |