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Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <common/debug.h>
9#include <drivers/arm/gicv2.h>
10#include <lib/mmio.h>
11#include <lib/psci/psci.h>
12#include <plat/common/platform.h>
13
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +080014#include "socfpga_mailbox.h"
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +080015#include "socfpga_plat_def.h"
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +080016#include "socfpga_reset_manager.h"
Hadi Asyrafi616da772019-06-27 11:34:03 +080017
Hadi Asyrafi616da772019-06-27 11:34:03 +080018
Hadi Asyrafi616da772019-06-27 11:34:03 +080019
20/*******************************************************************************
21 * plat handler called when a CPU is about to enter standby.
22 ******************************************************************************/
23void socfpga_cpu_standby(plat_local_state_t cpu_state)
24{
25 /*
26 * Enter standby state
27 * dsb is good practice before using wfi to enter low power states
28 */
29 VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
30 dsb();
31 wfi();
32}
33
34/*******************************************************************************
35 * plat handler called when a power domain is about to be turned on. The
36 * mpidr determines the CPU to be turned on.
37 ******************************************************************************/
38int socfpga_pwr_domain_on(u_register_t mpidr)
39{
40 unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
41
42 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
43
44 if (cpu_id == -1)
45 return PSCI_E_INTERN_FAIL;
46
Hadi Asyrafia2edf0e2019-10-22 13:39:14 +080047 mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
Hadi Asyrafi616da772019-06-27 11:34:03 +080048
49 /* release core reset */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +080050 mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
Hadi Asyrafi616da772019-06-27 11:34:03 +080051 return PSCI_E_SUCCESS;
52}
53
54/*******************************************************************************
55 * plat handler called when a power domain is about to be turned off. The
56 * target_state encodes the power state that each level should transition to.
57 ******************************************************************************/
58void socfpga_pwr_domain_off(const psci_power_state_t *target_state)
59{
Hadi Asyrafi616da772019-06-27 11:34:03 +080060 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
61 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
62 __func__, i, target_state->pwr_domain_state[i]);
63
Hadi Asyrafi91071fc2019-09-12 15:14:01 +080064 /* Prevent interrupts from spuriously waking up this cpu */
65 gicv2_cpuif_disable();
Hadi Asyrafi616da772019-06-27 11:34:03 +080066}
67
68/*******************************************************************************
69 * plat handler called when a power domain is about to be suspended. The
70 * target_state encodes the power state that each level should transition to.
71 ******************************************************************************/
72void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state)
73{
74 unsigned int cpu_id = plat_my_core_pos();
75
76 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
77 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
78 __func__, i, target_state->pwr_domain_state[i]);
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +080079
Hadi Asyrafi616da772019-06-27 11:34:03 +080080 /* assert core reset */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +080081 mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
Hadi Asyrafi616da772019-06-27 11:34:03 +080082
83}
84
85/*******************************************************************************
86 * plat handler called when a power domain has just been powered on after
87 * being turned off earlier. The target_state encodes the low power state that
88 * each level has woken up from.
89 ******************************************************************************/
90void socfpga_pwr_domain_on_finish(const psci_power_state_t *target_state)
91{
92 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
93 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
94 __func__, i, target_state->pwr_domain_state[i]);
95
96 /* Program the gic per-cpu distributor or re-distributor interface */
97 gicv2_pcpu_distif_init();
98 gicv2_set_pe_target_mask(plat_my_core_pos());
99
100 /* Enable the gic cpu interface */
101 gicv2_cpuif_enable();
102}
103
104/*******************************************************************************
105 * plat handler called when a power domain has just been powered on after
106 * having been suspended earlier. The target_state encodes the low power state
107 * that each level has woken up from.
108 * TODO: At the moment we reuse the on finisher and reinitialize the secure
109 * context. Need to implement a separate suspend finisher.
110 ******************************************************************************/
111void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
112{
113 unsigned int cpu_id = plat_my_core_pos();
114
115 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
116 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
117 __func__, i, target_state->pwr_domain_state[i]);
118
119 /* release core reset */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +0800120 mmio_clrbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800121}
122
123/*******************************************************************************
124 * plat handlers to shutdown/reboot the system
125 ******************************************************************************/
126static void __dead2 socfpga_system_off(void)
127{
128 wfi();
129 ERROR("System Off: operation not handled.\n");
130 panic();
131}
132
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800133extern uint64_t intel_rsu_update_address;
134
Hadi Asyrafi616da772019-06-27 11:34:03 +0800135static void __dead2 socfpga_system_reset(void)
136{
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +0800137 uint32_t addr_buf[2];
138
139 memcpy(addr_buf, &intel_rsu_update_address,
140 sizeof(intel_rsu_update_address));
141
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800142 if (intel_rsu_update_address)
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +0800143 mailbox_rsu_update(addr_buf);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800144 else
145 mailbox_reset_cold();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800146
147 while (1)
148 wfi();
149}
150
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800151static int socfpga_system_reset2(int is_vendor, int reset_type,
152 u_register_t cookie)
153{
154 /* disable cpuif */
155 gicv2_cpuif_disable();
156
157 /* Store magic number */
158 mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS);
159
160 /* Increase timeout */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +0800161 mmio_write_32(SOCFPGA_RSTMGR(HDSKTIMEOUT), 0xffffff);
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800162
163 /* Enable handshakes */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +0800164 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET);
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800165
166 /* Reset L2 module */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +0800167 mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100);
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800168
169 while (1)
170 wfi();
171
172 /* Should not reach here */
173 return 0;
174}
175
Hadi Asyrafi616da772019-06-27 11:34:03 +0800176int socfpga_validate_power_state(unsigned int power_state,
177 psci_power_state_t *req_state)
178{
179 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
180
181 return PSCI_E_SUCCESS;
182}
183
184int socfpga_validate_ns_entrypoint(unsigned long ns_entrypoint)
185{
186 VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint);
187 return PSCI_E_SUCCESS;
188}
189
190void socfpga_get_sys_suspend_power_state(psci_power_state_t *req_state)
191{
192 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
193 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
194}
195
196/*******************************************************************************
197 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
198 * platform layer will take care of registering the handlers with PSCI.
199 ******************************************************************************/
200const plat_psci_ops_t socfpga_psci_pm_ops = {
201 .cpu_standby = socfpga_cpu_standby,
202 .pwr_domain_on = socfpga_pwr_domain_on,
203 .pwr_domain_off = socfpga_pwr_domain_off,
204 .pwr_domain_suspend = socfpga_pwr_domain_suspend,
205 .pwr_domain_on_finish = socfpga_pwr_domain_on_finish,
206 .pwr_domain_suspend_finish = socfpga_pwr_domain_suspend_finish,
207 .system_off = socfpga_system_off,
208 .system_reset = socfpga_system_reset,
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800209 .system_reset2 = socfpga_system_reset2,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800210 .validate_power_state = socfpga_validate_power_state,
211 .validate_ns_entrypoint = socfpga_validate_ns_entrypoint,
212 .get_sys_suspend_power_state = socfpga_get_sys_suspend_power_state
213};
214
215/*******************************************************************************
216 * Export the platform specific power ops.
217 ******************************************************************************/
218int plat_setup_psci_ops(uintptr_t sec_entrypoint,
219 const struct plat_psci_ops **psci_ops)
220{
221 /* Save warm boot entrypoint.*/
Hadi Asyrafia2edf0e2019-10-22 13:39:14 +0800222 mmio_write_64(PLAT_SEC_ENTRY, sec_entrypoint);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800223 *psci_ops = &socfpga_psci_pm_ops;
Hadi Asyrafia2edf0e2019-10-22 13:39:14 +0800224
Hadi Asyrafi616da772019-06-27 11:34:03 +0800225 return 0;
226}