blob: d4dd0af7dbfa0ae3c090ef06a077a048b1d39eb3 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vikram Kanigirifbb13012016-02-15 11:54:14 +00002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley9df48042015-03-19 18:58:55 +000031#include <arch_helpers.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +010032#include <assert.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +010033#include <cassert.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +010034#include <css_pm.h>
Dan Handley9df48042015-03-19 18:58:55 +000035#include <debug.h>
36#include <errno.h>
37#include <plat_arm.h>
38#include <platform.h>
39#include <platform_def.h>
Soby Mathew200fffd2016-10-21 11:34:59 +010040#include "../drivers/scp/css_scp.h"
Soby Mathew12012dd2015-10-26 14:01:53 +000041
Soby Mathewfeac8fc2015-09-29 15:47:16 +010042/* Allow CSS platforms to override `plat_arm_psci_pm_ops` */
43#pragma weak plat_arm_psci_pm_ops
Soby Mathewfec4eb72015-07-01 16:16:20 +010044
Soby Mathew7799cf72015-04-16 14:49:09 +010045#if ARM_RECOM_STATE_ID_ENC
46/*
47 * The table storing the valid idle power states. Ensure that the
48 * array entries are populated in ascending order of state-id to
49 * enable us to use binary search during power state validation.
50 * The table must be terminated by a NULL entry.
51 */
52const unsigned int arm_pm_idle_states[] = {
Soby Mathewa869de12015-05-08 10:18:59 +010053 /* State-id - 0x001 */
54 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
55 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
56 /* State-id - 0x002 */
57 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
58 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
59 /* State-id - 0x022 */
60 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
61 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
62#if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
63 /* State-id - 0x222 */
64 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
65 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
66#endif
Soby Mathew7799cf72015-04-16 14:49:09 +010067 0,
68};
Soby Mathewa869de12015-05-08 10:18:59 +010069#endif /* __ARM_RECOM_STATE_ID_ENC__ */
Soby Mathew7799cf72015-04-16 14:49:09 +010070
Soby Mathew61e8d0b2015-10-12 17:32:29 +010071/*
72 * All the power management helpers in this file assume at least cluster power
73 * level is supported.
74 */
75CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
76 assert_max_pwr_lvl_supported_mismatch);
77
Dan Handley9df48042015-03-19 18:58:55 +000078/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +010079 * Handler called when a power domain is about to be turned on. The
Dan Handley9df48042015-03-19 18:58:55 +000080 * level and mpidr determine the affinity instance.
81 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +010082int css_pwr_domain_on(u_register_t mpidr)
Dan Handley9df48042015-03-19 18:58:55 +000083{
Soby Mathew200fffd2016-10-21 11:34:59 +010084 css_scp_on(mpidr);
Dan Handley9df48042015-03-19 18:58:55 +000085
86 return PSCI_E_SUCCESS;
87}
88
Soby Mathew12012dd2015-10-26 14:01:53 +000089static void css_pwr_domain_on_finisher_common(
90 const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +000091{
Soby Mathew12012dd2015-10-26 14:01:53 +000092 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathew61e8d0b2015-10-12 17:32:29 +010093
Dan Handley9df48042015-03-19 18:58:55 +000094 /*
95 * Perform the common cluster specific operations i.e enable coherency
96 * if this cluster was off.
97 */
Soby Mathew12012dd2015-10-26 14:01:53 +000098 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
Vikram Kanigirifbb13012016-02-15 11:54:14 +000099 plat_arm_interconnect_enter_coherency();
Soby Mathew12012dd2015-10-26 14:01:53 +0000100}
Dan Handley9df48042015-03-19 18:58:55 +0000101
Soby Mathew12012dd2015-10-26 14:01:53 +0000102/*******************************************************************************
103 * Handler called when a power level has just been powered on after
104 * being turned off earlier. The target_state encodes the low power state that
105 * each level has woken up from. This handler would never be invoked with
106 * the system power domain uninitialized as either the primary would have taken
107 * care of it as part of cold boot or the first core awakened from system
108 * suspend would have already initialized it.
109 ******************************************************************************/
110void css_pwr_domain_on_finish(const psci_power_state_t *target_state)
111{
112 /* Assert that the system power domain need not be initialized */
113 assert(CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_RUN);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100114
Soby Mathew12012dd2015-10-26 14:01:53 +0000115 css_pwr_domain_on_finisher_common(target_state);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100116
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000117 /* Program the gic per-cpu distributor or re-distributor interface */
118 plat_arm_gic_pcpu_init();
119
Dan Handley9df48042015-03-19 18:58:55 +0000120 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000121 plat_arm_gic_cpuif_enable();
Dan Handley9df48042015-03-19 18:58:55 +0000122}
123
124/*******************************************************************************
125 * Common function called while turning a cpu off or suspending it. It is called
126 * from css_off() or css_suspend() when these functions in turn are called for
Soby Mathewfec4eb72015-07-01 16:16:20 +0100127 * power domain at the highest power level which will be powered down. It
128 * performs the actions common to the OFF and SUSPEND calls.
Dan Handley9df48042015-03-19 18:58:55 +0000129 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100130static void css_power_down_common(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000131{
Dan Handley9df48042015-03-19 18:58:55 +0000132 /* Prevent interrupts from spuriously waking up this cpu */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000133 plat_arm_gic_cpuif_disable();
Dan Handley9df48042015-03-19 18:58:55 +0000134
135 /* Cluster is to be turned off, so disable coherency */
Soby Mathew200fffd2016-10-21 11:34:59 +0100136 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000137 plat_arm_interconnect_exit_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000138}
139
140/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100141 * Handler called when a power domain is about to be turned off. The
142 * target_state encodes the power state that each level should transition to.
Dan Handley9df48042015-03-19 18:58:55 +0000143 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100144void css_pwr_domain_off(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000145{
Soby Mathew12012dd2015-10-26 14:01:53 +0000146 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100147 css_power_down_common(target_state);
Soby Mathew200fffd2016-10-21 11:34:59 +0100148 css_scp_off(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000149}
150
151/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100152 * Handler called when a power domain is about to be suspended. The
153 * target_state encodes the power state that each level should transition to.
Dan Handley9df48042015-03-19 18:58:55 +0000154 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100155void css_pwr_domain_suspend(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000156{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100157 /*
Soby Mathew12012dd2015-10-26 14:01:53 +0000158 * CSS currently supports retention only at cpu level. Just return
Soby Mathewfec4eb72015-07-01 16:16:20 +0100159 * as nothing is to be done for retention.
160 */
Soby Mathew12012dd2015-10-26 14:01:53 +0000161 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
Dan Handley9df48042015-03-19 18:58:55 +0000162 return;
163
Soby Mathew12012dd2015-10-26 14:01:53 +0000164 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100165 css_power_down_common(target_state);
Soby Mathew200fffd2016-10-21 11:34:59 +0100166 css_scp_suspend(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000167}
168
169/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100170 * Handler called when a power domain has just been powered on after
171 * having been suspended earlier. The target_state encodes the low power state
172 * that each level has woken up from.
Dan Handley9df48042015-03-19 18:58:55 +0000173 * TODO: At the moment we reuse the on finisher and reinitialize the secure
174 * context. Need to implement a separate suspend finisher.
175 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100176void css_pwr_domain_suspend_finish(
Soby Mathewfec4eb72015-07-01 16:16:20 +0100177 const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000178{
Soby Mathew12012dd2015-10-26 14:01:53 +0000179 /* Return as nothing is to be done on waking up from retention. */
180 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
Soby Mathewfec4eb72015-07-01 16:16:20 +0100181 return;
182
Soby Mathew12012dd2015-10-26 14:01:53 +0000183 /* Perform system domain restore if woken up from system suspend */
184 if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
185 arm_system_pwr_domain_resume();
186 else
187 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000188 plat_arm_gic_cpuif_enable();
Soby Mathew12012dd2015-10-26 14:01:53 +0000189
190 css_pwr_domain_on_finisher_common(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000191}
192
193/*******************************************************************************
194 * Handlers to shutdown/reboot the system
195 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100196void __dead2 css_system_off(void)
Dan Handley9df48042015-03-19 18:58:55 +0000197{
Soby Mathew200fffd2016-10-21 11:34:59 +0100198 css_scp_sys_shutdown();
Dan Handley9df48042015-03-19 18:58:55 +0000199}
200
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100201void __dead2 css_system_reset(void)
Dan Handley9df48042015-03-19 18:58:55 +0000202{
Soby Mathew200fffd2016-10-21 11:34:59 +0100203 css_scp_sys_reboot();
Dan Handley9df48042015-03-19 18:58:55 +0000204}
205
206/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100207 * Handler called when the CPU power domain is about to enter standby.
Dan Handley9df48042015-03-19 18:58:55 +0000208 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100209void css_cpu_standby(plat_local_state_t cpu_state)
Dan Handley9df48042015-03-19 18:58:55 +0000210{
211 unsigned int scr;
212
Soby Mathewfec4eb72015-07-01 16:16:20 +0100213 assert(cpu_state == ARM_LOCAL_STATE_RET);
214
Dan Handley9df48042015-03-19 18:58:55 +0000215 scr = read_scr_el3();
David Wangc1d9cfb2016-06-07 09:22:40 +0800216 /*
217 * Enable the Non secure interrupt to wake the CPU.
218 * In GICv3 affinity routing mode, the non secure group1 interrupts use
219 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ.
220 * Enabling both the bits works for both GICv2 mode and GICv3 affinity
221 * routing mode.
222 */
223 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
Dan Handley9df48042015-03-19 18:58:55 +0000224 isb();
225 dsb();
226 wfi();
227
228 /*
229 * Restore SCR to the original value, synchronisation of scr_el3 is
230 * done by eret while el3_exit to save some execution cycles.
231 */
232 write_scr_el3(scr);
233}
234
235/*******************************************************************************
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100236 * Handler called to return the 'req_state' for system suspend.
237 ******************************************************************************/
238void css_get_sys_suspend_power_state(psci_power_state_t *req_state)
239{
240 unsigned int i;
241
242 /*
243 * System Suspend is supported only if the system power domain node
244 * is implemented.
245 */
246 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
247
248 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
249 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
250}
251
252/*******************************************************************************
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100253 * Handler to query CPU/cluster power states from SCP
254 ******************************************************************************/
255int css_node_hw_state(u_register_t mpidr, unsigned int power_level)
256{
Soby Mathew200fffd2016-10-21 11:34:59 +0100257 return css_scp_get_power_state(mpidr, power_level);
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100258}
259
260/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100261 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
262 * platform will take care of registering the handlers with PSCI.
Dan Handley9df48042015-03-19 18:58:55 +0000263 ******************************************************************************/
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100264plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100265 .pwr_domain_on = css_pwr_domain_on,
266 .pwr_domain_on_finish = css_pwr_domain_on_finish,
267 .pwr_domain_off = css_pwr_domain_off,
268 .cpu_standby = css_cpu_standby,
269 .pwr_domain_suspend = css_pwr_domain_suspend,
270 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish,
Dan Handley9df48042015-03-19 18:58:55 +0000271 .system_off = css_system_off,
272 .system_reset = css_system_reset,
Soby Mathew0d9e8522015-07-15 13:36:24 +0100273 .validate_power_state = arm_validate_power_state,
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100274 .validate_ns_entrypoint = arm_validate_ns_entrypoint,
275 .get_node_hw_state = css_node_hw_state
Dan Handley9df48042015-03-19 18:58:55 +0000276};