| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 1 | # |
| Varun Wadekar | 9f4a7d3 | 2018-10-19 11:42:28 -0700 | [diff] [blame] | 2 | # Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 3 | # |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | # SPDX-License-Identifier: BSD-3-Clause |
| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 5 | # |
| 6 | |
| Varun Wadekar | e98a146 | 2015-07-31 10:15:41 +0530 | [diff] [blame] | 7 | TZDRAM_BASE := 0xF5C00000 |
| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 8 | $(eval $(call add_define,TZDRAM_BASE)) |
| 9 | |
| 10 | PLATFORM_CLUSTER_COUNT := 1 |
| 11 | $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) |
| 12 | |
| 13 | PLATFORM_MAX_CPUS_PER_CLUSTER := 2 |
| 14 | $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) |
| 15 | |
| Varun Wadekar | 97f2490 | 2015-09-09 11:29:24 +0530 | [diff] [blame] | 16 | MAX_XLAT_TABLES := 3 |
| 17 | $(eval $(call add_define,MAX_XLAT_TABLES)) |
| 18 | |
| 19 | MAX_MMAP_REGIONS := 8 |
| 20 | $(eval $(call add_define,MAX_MMAP_REGIONS)) |
| 21 | |
| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 22 | BL31_SOURCES += lib/cpus/aarch64/denver.S \ |
| Varun Wadekar | a1176ba | 2015-08-25 17:01:06 +0530 | [diff] [blame] | 23 | ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ |
| Varun Wadekar | 7a9a285 | 2015-09-18 11:21:22 +0530 | [diff] [blame] | 24 | ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \ |
| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 25 | ${SOC_DIR}/plat_psci_handlers.c \ |
| Varun Wadekar | cbdace1 | 2015-09-03 14:32:44 +0530 | [diff] [blame] | 26 | ${SOC_DIR}/plat_sip_calls.c \ |
| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 27 | ${SOC_DIR}/plat_setup.c \ |
| 28 | ${SOC_DIR}/plat_secondary.c |