| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 1 | # |
| 2 | # Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | # |
| 4 | # Redistribution and use in source and binary forms, with or without |
| 5 | # modification, are permitted provided that the following conditions are met: |
| 6 | # |
| 7 | # Redistributions of source code must retain the above copyright notice, this |
| 8 | # list of conditions and the following disclaimer. |
| 9 | # |
| 10 | # Redistributions in binary form must reproduce the above copyright notice, |
| 11 | # this list of conditions and the following disclaimer in the documentation |
| 12 | # and/or other materials provided with the distribution. |
| 13 | # |
| 14 | # Neither the name of ARM nor the names of its contributors may be used |
| 15 | # to endorse or promote products derived from this software without specific |
| 16 | # prior written permission. |
| 17 | # |
| 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | # POSSIBILITY OF SUCH DAMAGE. |
| 29 | # |
| 30 | |
| 31 | TEGRA_BOOT_UART_BASE := 0x70006300 |
| 32 | $(eval $(call add_define,TEGRA_BOOT_UART_BASE)) |
| 33 | |
| Varun Wadekar | e98a146 | 2015-07-31 10:15:41 +0530 | [diff] [blame] | 34 | TZDRAM_BASE := 0xF5C00000 |
| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 35 | $(eval $(call add_define,TZDRAM_BASE)) |
| 36 | |
| 37 | PLATFORM_CLUSTER_COUNT := 1 |
| 38 | $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) |
| 39 | |
| 40 | PLATFORM_MAX_CPUS_PER_CLUSTER := 2 |
| 41 | $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) |
| 42 | |
| Varun Wadekar | 97f2490 | 2015-09-09 11:29:24 +0530 | [diff] [blame^] | 43 | MAX_XLAT_TABLES := 3 |
| 44 | $(eval $(call add_define,MAX_XLAT_TABLES)) |
| 45 | |
| 46 | MAX_MMAP_REGIONS := 8 |
| 47 | $(eval $(call add_define,MAX_MMAP_REGIONS)) |
| 48 | |
| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 49 | BL31_SOURCES += lib/cpus/aarch64/denver.S \ |
| Varun Wadekar | a1176ba | 2015-08-25 17:01:06 +0530 | [diff] [blame] | 50 | ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ |
| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 51 | ${SOC_DIR}/plat_psci_handlers.c \ |
| Varun Wadekar | cbdace1 | 2015-09-03 14:32:44 +0530 | [diff] [blame] | 52 | ${SOC_DIR}/plat_sip_calls.c \ |
| Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 53 | ${SOC_DIR}/plat_setup.c \ |
| 54 | ${SOC_DIR}/plat_secondary.c |