Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 1 | # |
Chris Kay | 523e864 | 2023-12-04 12:03:51 +0000 | [diff] [blame] | 2 | # Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
| 7 | include lib/libfdt/libfdt.mk |
| 8 | include lib/xlat_tables_v2/xlat_tables.mk |
| 9 | |
Jan Kiszka | cdd95e7 | 2021-03-22 20:42:33 +0100 | [diff] [blame] | 10 | include drivers/arm/gic/v2/gicv2.mk |
| 11 | |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 12 | PLAT_INCLUDES := -Iplat/rpi/common/include \ |
| 13 | -Iplat/rpi/rpi4/include |
| 14 | |
| 15 | PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ |
Andre Przywara | 9ba6bb0 | 2020-03-10 12:34:56 +0000 | [diff] [blame] | 16 | drivers/arm/pl011/aarch64/pl011_console.S \ |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 17 | plat/rpi/common/rpi3_common.c \ |
| 18 | ${XLAT_TABLES_LIB_SRCS} |
| 19 | |
| 20 | BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \ |
Andre Przywara | 98e4856 | 2020-03-12 14:20:04 +0000 | [diff] [blame] | 21 | plat/rpi/common/aarch64/plat_helpers.S \ |
Andre Przywara | 2d8e99a | 2019-07-10 18:09:18 +0100 | [diff] [blame] | 22 | plat/rpi/rpi4/aarch64/armstub8_header.S \ |
Andre Przywara | 980556d | 2020-03-11 15:18:03 +0000 | [diff] [blame] | 23 | drivers/delay_timer/delay_timer.c \ |
| 24 | drivers/gpio/gpio.c \ |
| 25 | drivers/rpi3/gpio/rpi3_gpio.c \ |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 26 | plat/common/plat_gicv2.c \ |
| 27 | plat/rpi/rpi4/rpi4_bl31_setup.c \ |
| 28 | plat/rpi/common/rpi3_pm.c \ |
| 29 | plat/common/plat_psci_common.c \ |
| 30 | plat/rpi/common/rpi3_topology.c \ |
Andre Przywara | 88c9e1d | 2019-07-11 01:45:39 +0100 | [diff] [blame] | 31 | common/fdt_fixup.c \ |
Jan Kiszka | cdd95e7 | 2021-03-22 20:42:33 +0100 | [diff] [blame] | 32 | ${LIBFDT_SRCS} \ |
| 33 | ${GICV2_SOURCES} |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 34 | |
| 35 | # For now we only support BL31, using the kernel loaded by the GPU firmware. |
| 36 | RESET_TO_BL31 := 1 |
| 37 | |
| 38 | # All CPUs enter armstub8.bin. |
| 39 | COLD_BOOT_SINGLE_CPU := 0 |
| 40 | |
| 41 | # Tune compiler for Cortex-A72 |
Chris Kay | cfba645 | 2023-12-04 09:55:50 +0000 | [diff] [blame] | 42 | ifeq ($($(ARCH)-cc-id),arm-clang) |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 43 | TF_CFLAGS_aarch64 += -mcpu=cortex-a72 |
Chris Kay | cfba645 | 2023-12-04 09:55:50 +0000 | [diff] [blame] | 44 | else ifneq ($(filter %-clang,$($(ARCH)-cc-id)),) |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 45 | TF_CFLAGS_aarch64 += -mcpu=cortex-a72 |
| 46 | else |
| 47 | TF_CFLAGS_aarch64 += -mtune=cortex-a72 |
| 48 | endif |
| 49 | |
Andre Przywara | 2d8e99a | 2019-07-10 18:09:18 +0100 | [diff] [blame] | 50 | # Add support for platform supplied linker script for BL31 build |
| 51 | $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 52 | |
| 53 | # Enable all errata workarounds for Cortex-A72 |
| 54 | ERRATA_A72_859971 := 1 |
| 55 | |
| 56 | WORKAROUND_CVE_2017_5715 := 1 |
| 57 | |
| 58 | # Add new default target when compiling this platform |
| 59 | all: bl31 |
| 60 | |
| 61 | # Build config flags |
| 62 | # ------------------ |
| 63 | |
| 64 | # Disable stack protector by default |
| 65 | ENABLE_STACK_PROTECTOR := 0 |
| 66 | |
| 67 | # Have different sections for code and rodata |
| 68 | SEPARATE_CODE_AND_RODATA := 1 |
| 69 | |
| 70 | # Use Coherent memory |
| 71 | USE_COHERENT_MEM := 1 |
| 72 | |
| 73 | # Platform build flags |
| 74 | # -------------------- |
| 75 | |
Andre Przywara | aa89ae4 | 2019-07-11 01:42:12 +0100 | [diff] [blame] | 76 | # There is not much else than a Linux kernel to load at the moment. |
| 77 | RPI3_DIRECT_LINUX_BOOT := 1 |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 78 | |
| 79 | # BL33 images are in AArch64 by default |
| 80 | RPI3_BL33_IN_AARCH32 := 0 |
| 81 | |
| 82 | # UART to use at runtime. -1 means the runtime UART is disabled. |
| 83 | # Any other value means the default UART will be used. |
| 84 | RPI3_RUNTIME_UART := 0 |
| 85 | |
| 86 | # Use normal memory mapping for ROM, FIP, SRAM and DRAM |
| 87 | RPI3_USE_UEFI_MAP := 0 |
| 88 | |
Jeremy Linton | 15242d5 | 2020-11-18 10:13:30 -0600 | [diff] [blame] | 89 | # SMCCC PCI support (should be enabled for ACPI builds) |
| 90 | SMC_PCI_SUPPORT := 0 |
| 91 | |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 92 | # Process platform flags |
| 93 | # ---------------------- |
| 94 | |
| 95 | $(eval $(call add_define,RPI3_BL33_IN_AARCH32)) |
| 96 | $(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT)) |
| 97 | ifdef RPI3_PRELOADED_DTB_BASE |
| 98 | $(eval $(call add_define,RPI3_PRELOADED_DTB_BASE)) |
| 99 | endif |
| 100 | $(eval $(call add_define,RPI3_RUNTIME_UART)) |
| 101 | $(eval $(call add_define,RPI3_USE_UEFI_MAP)) |
Jeremy Linton | 15242d5 | 2020-11-18 10:13:30 -0600 | [diff] [blame] | 102 | $(eval $(call add_define,SMC_PCI_SUPPORT)) |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 103 | |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 104 | ifeq (${ARCH},aarch32) |
| 105 | $(error Error: AArch32 not supported on rpi4) |
| 106 | endif |
| 107 | |
| 108 | ifneq ($(ENABLE_STACK_PROTECTOR), 0) |
| 109 | PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \ |
| 110 | plat/rpi/common/rpi3_stack_protector.c |
| 111 | endif |
Jeremy Linton | 15242d5 | 2020-11-18 10:13:30 -0600 | [diff] [blame] | 112 | |
| 113 | ifeq ($(SMC_PCI_SUPPORT), 1) |
| 114 | BL31_SOURCES += plat/rpi/rpi4/rpi4_pci_svc.c |
| 115 | endif |