johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
Harrison Mutai | ac05cb4 | 2023-04-25 11:47:49 +0100 | [diff] [blame] | 2 | * Copyright (c) 2021-2023, Arm Limited. All rights reserved. |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a710.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
| 17 | #error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 18 | #endif |
| 19 | |
| 20 | /* 64-bit only core */ |
| 21 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 22 | #error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 23 | #endif |
| 24 | |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 25 | #if WORKAROUND_CVE_2022_23960 |
| 26 | wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 |
| 27 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 28 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 29 | workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 30 | ldr x0,=0x6 |
| 31 | msr S3_6_c15_c8_0,x0 |
| 32 | ldr x0,=0xF3A08002 |
| 33 | msr S3_6_c15_c8_2,x0 |
| 34 | ldr x0,=0xFFF0F7FE |
| 35 | msr S3_6_c15_c8_3,x0 |
| 36 | ldr x0,=0x40000001003ff |
| 37 | msr S3_6_c15_c8_1,x0 |
| 38 | ldr x0,=0x7 |
| 39 | msr S3_6_c15_c8_0,x0 |
| 40 | ldr x0,=0xBF200000 |
| 41 | msr S3_6_c15_c8_2,x0 |
| 42 | ldr x0,=0xFFEF0000 |
| 43 | msr S3_6_c15_c8_3,x0 |
| 44 | ldr x0,=0x40000001003f3 |
| 45 | msr S3_6_c15_c8_1,x0 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 46 | workaround_reset_end cortex_a710, ERRATUM(1987031) |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 47 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 48 | check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) |
nayanpatel-arm | 7597d08 | 2021-08-25 17:35:15 -0700 | [diff] [blame] | 49 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 50 | workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 |
Harrison Mutai | ac05cb4 | 2023-04-25 11:47:49 +0100 | [diff] [blame] | 51 | /* Stash ERRSELR_EL1 in x2 */ |
| 52 | mrs x2, ERRSELR_EL1 |
nayanpatel-arm | 7597d08 | 2021-08-25 17:35:15 -0700 | [diff] [blame] | 53 | |
Harrison Mutai | ac05cb4 | 2023-04-25 11:47:49 +0100 | [diff] [blame] | 54 | /* Select error record 0 and clear ED bit */ |
| 55 | msr ERRSELR_EL1, xzr |
| 56 | mrs x1, ERXCTLR_EL1 |
| 57 | bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 |
| 58 | msr ERXCTLR_EL1, x1 |
nayanpatel-arm | 7597d08 | 2021-08-25 17:35:15 -0700 | [diff] [blame] | 59 | |
Harrison Mutai | ac05cb4 | 2023-04-25 11:47:49 +0100 | [diff] [blame] | 60 | /* Select error record 1 and clear ED bit */ |
| 61 | mov x0, #1 |
| 62 | msr ERRSELR_EL1, x0 |
| 63 | mrs x1, ERXCTLR_EL1 |
| 64 | bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 |
| 65 | msr ERXCTLR_EL1, x1 |
| 66 | |
| 67 | /* Restore ERRSELR_EL1 from x2 */ |
| 68 | msr ERRSELR_EL1, x2 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 69 | workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB |
Harrison Mutai | ac05cb4 | 2023-04-25 11:47:49 +0100 | [diff] [blame] | 70 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 71 | check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 72 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 73 | workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 74 | sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 75 | workaround_reset_end cortex_a710, ERRATUM(2017096) |
Bipin Ravi | 87e1d28 | 2021-03-31 18:45:55 -0500 | [diff] [blame] | 76 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 77 | check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) |
Bipin Ravi | 87e1d28 | 2021-03-31 18:45:55 -0500 | [diff] [blame] | 78 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 79 | workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 80 | sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 81 | workaround_reset_end cortex_a710, ERRATUM(2055002) |
nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 82 | |
Sona Mathew | 6d691c5 | 2023-10-10 13:51:45 -0500 | [diff] [blame] | 83 | check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) |
nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 84 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 85 | workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056 |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 86 | sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \ |
| 87 | CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 88 | workaround_reset_end cortex_a710, ERRATUM(2058056) |
nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 89 | |
Sona Mathew | 6d691c5 | 2023-10-10 13:51:45 -0500 | [diff] [blame] | 90 | check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1) |
nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 91 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 92 | workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 |
Harrison Mutai | ac05cb4 | 2023-04-25 11:47:49 +0100 | [diff] [blame] | 93 | ldr x0,=0x3 |
| 94 | msr S3_6_c15_c8_0,x0 |
| 95 | ldr x0,=0xF3A08002 |
| 96 | msr S3_6_c15_c8_2,x0 |
| 97 | ldr x0,=0xFFF0F7FE |
| 98 | msr S3_6_c15_c8_3,x0 |
| 99 | ldr x0,=0x10002001003FF |
| 100 | msr S3_6_c15_c8_1,x0 |
| 101 | ldr x0,=0x4 |
| 102 | msr S3_6_c15_c8_0,x0 |
| 103 | ldr x0,=0xBF200000 |
| 104 | msr S3_6_c15_c8_2,x0 |
| 105 | ldr x0,=0xFFEF0000 |
| 106 | msr S3_6_c15_c8_3,x0 |
| 107 | ldr x0,=0x10002001003F3 |
| 108 | msr S3_6_c15_c8_1,x0 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 109 | workaround_reset_end cortex_a710, ERRATUM(2081180) |
Bipin Ravi | 32705b1 | 2022-02-06 02:32:54 -0600 | [diff] [blame] | 110 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 111 | check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) |
Harrison Mutai | ac05cb4 | 2023-04-25 11:47:49 +0100 | [diff] [blame] | 112 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 113 | workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 114 | sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 115 | workaround_reset_end cortex_a710, ERRATUM(2083908) |
Harrison Mutai | ac05cb4 | 2023-04-25 11:47:49 +0100 | [diff] [blame] | 116 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 117 | check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) |
Bipin Ravi | 32705b1 | 2022-02-06 02:32:54 -0600 | [diff] [blame] | 118 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 119 | workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 120 | sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 121 | workaround_reset_end cortex_a710, ERRATUM(2136059) |
Bipin Ravi | d53069b | 2022-02-06 03:11:44 -0600 | [diff] [blame] | 122 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 123 | check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) |
Bipin Ravi | d53069b | 2022-02-06 03:11:44 -0600 | [diff] [blame] | 124 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 125 | workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 126 | sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 127 | workaround_reset_end cortex_a710, ERRATUM(2147715) |
Akram Ahmad | 1714c1d | 2022-07-21 15:25:08 +0100 | [diff] [blame] | 128 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 129 | check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) |
Jayanth Dodderi Chidanand | de4f589 | 2022-09-01 22:09:54 +0100 | [diff] [blame] | 130 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 131 | workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 132 | sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 |
Jayanth Dodderi Chidanand | de4f589 | 2022-09-01 22:09:54 +0100 | [diff] [blame] | 133 | |
| 134 | ldr x0,=0x5 |
| 135 | msr CORTEX_A710_CPUPSELR_EL3, x0 |
| 136 | ldr x0,=0x10F600E000 |
| 137 | msr CORTEX_A710_CPUPOR_EL3, x0 |
| 138 | ldr x0,=0x10FF80E000 |
| 139 | msr CORTEX_A710_CPUPMR_EL3, x0 |
| 140 | ldr x0,=0x80000000003FF |
| 141 | msr CORTEX_A710_CPUPCR_EL3, x0 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 142 | workaround_reset_end cortex_a710, ERRATUM(2216384) |
Jayanth Dodderi Chidanand | de4f589 | 2022-09-01 22:09:54 +0100 | [diff] [blame] | 143 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 144 | check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) |
Jayanth Dodderi Chidanand | de4f589 | 2022-09-01 22:09:54 +0100 | [diff] [blame] | 145 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 146 | workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 147 | sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 148 | workaround_reset_end cortex_a710, ERRATUM(2267065) |
Harrison Mutai | ac05cb4 | 2023-04-25 11:47:49 +0100 | [diff] [blame] | 149 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 150 | check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) |
Harrison Mutai | ac05cb4 | 2023-04-25 11:47:49 +0100 | [diff] [blame] | 151 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 152 | workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 153 | sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 154 | workaround_reset_end cortex_a710, ERRATUM(2282622) |
johpow01 | 7249fd0 | 2022-02-28 18:34:04 -0600 | [diff] [blame] | 155 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 156 | check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) |
johpow01 | 7249fd0 | 2022-02-28 18:34:04 -0600 | [diff] [blame] | 157 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 158 | workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 |
Boyan Karatotev | f8de535 | 2022-10-03 14:21:28 +0100 | [diff] [blame] | 159 | /* Set bit 36 in ACTLR2_EL1 */ |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 160 | sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 161 | workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB |
Boyan Karatotev | f8de535 | 2022-10-03 14:21:28 +0100 | [diff] [blame] | 162 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 163 | check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) |
Boyan Karatotev | f8de535 | 2022-10-03 14:21:28 +0100 | [diff] [blame] | 164 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 165 | /* |
| 166 | * ERRATA_DSU_2313941 is defined in dsu_helpers.S but applies to Cortex-A710 as |
| 167 | * well. Create a symbollic link to existing errata workaround to get them |
| 168 | * registered under the Errata Framework. |
Bipin Ravi | 77eab29 | 2022-07-12 15:53:21 -0500 | [diff] [blame] | 169 | */ |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 170 | .equ check_erratum_cortex_a710_2313941, check_errata_dsu_2313941 |
| 171 | .equ erratum_cortex_a710_2313941_wa, errata_dsu_2313941_wa |
| 172 | add_erratum_entry cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET |
Bipin Ravi | 77eab29 | 2022-07-12 15:53:21 -0500 | [diff] [blame] | 173 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 174 | workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 |
Bipin Ravi | 77eab29 | 2022-07-12 15:53:21 -0500 | [diff] [blame] | 175 | /* Set bit 40 in CPUACTLR2_EL1 */ |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 176 | sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 177 | workaround_reset_end cortex_a710, ERRATUM(2371105) |
Bipin Ravi | 77eab29 | 2022-07-12 15:53:21 -0500 | [diff] [blame] | 178 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 179 | check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) |
Bipin Ravi | 77eab29 | 2022-07-12 15:53:21 -0500 | [diff] [blame] | 180 | |
Bipin Ravi | bfa1468 | 2023-10-17 07:55:55 -0500 | [diff] [blame] | 181 | workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 |
| 182 | /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ |
| 183 | sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) |
| 184 | sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) |
| 185 | workaround_reset_end cortex_a710, ERRATUM(2742423) |
| 186 | |
| 187 | check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) |
| 188 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 189 | workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 |
Bipin Ravi | ef9a155 | 2022-12-07 13:32:35 -0600 | [diff] [blame] | 190 | /* dsb before isb of power down sequence */ |
| 191 | dsb sy |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 192 | workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB |
Bipin Ravi | ef9a155 | 2022-12-07 13:32:35 -0600 | [diff] [blame] | 193 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 194 | check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) |
Bipin Ravi | ef9a155 | 2022-12-07 13:32:35 -0600 | [diff] [blame] | 195 | |
Sona Mathew | e2fea18 | 2023-12-08 20:52:17 -0600 | [diff] [blame] | 196 | workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 |
| 197 | sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) |
| 198 | workaround_reset_end cortex_a710, ERRATUM(2778471) |
| 199 | |
| 200 | check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) |
| 201 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 202 | workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 203 | #if IMAGE_BL31 |
| 204 | /* |
| 205 | * The Cortex-A710 generic vectors are overridden to apply errata |
| 206 | * mitigation on exception entry from lower ELs. |
| 207 | */ |
Harrison Mutai | 1eb3038 | 2023-05-04 13:57:33 +0100 | [diff] [blame] | 208 | override_vector_table wa_cve_vbar_cortex_a710 |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 209 | #endif /* IMAGE_BL31 */ |
| 210 | workaround_reset_end cortex_a710, CVE(2022, 23960) |
| 211 | |
| 212 | check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 213 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 214 | /* ---------------------------------------------------- |
| 215 | * HW will do the cache maintenance while powering down |
| 216 | * ---------------------------------------------------- |
| 217 | */ |
| 218 | func cortex_a710_core_pwr_dwn |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 219 | apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 |
| 220 | apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV |
Boyan Karatotev | f8de535 | 2022-10-03 14:21:28 +0100 | [diff] [blame] | 221 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 222 | /* --------------------------------------------------- |
| 223 | * Enable CPU power down bit in power control register |
| 224 | * --------------------------------------------------- |
| 225 | */ |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 226 | sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 227 | apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 228 | isb |
| 229 | ret |
| 230 | endfunc cortex_a710_core_pwr_dwn |
| 231 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 232 | errata_report_shim cortex_a710 |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 233 | |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 234 | cpu_reset_func_start cortex_a710 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 235 | /* Disable speculative loads */ |
| 236 | msr SSBS, xzr |
Harrison Mutai | 14b1c12 | 2023-04-26 12:18:46 +0100 | [diff] [blame] | 237 | cpu_reset_func_end cortex_a710 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 238 | |
| 239 | /* --------------------------------------------- |
| 240 | * This function provides Cortex-A710 specific |
| 241 | * register information for crash reporting. |
| 242 | * It needs to return with x6 pointing to |
| 243 | * a list of register names in ascii and |
| 244 | * x8 - x15 having values of registers to be |
| 245 | * reported. |
| 246 | * --------------------------------------------- |
| 247 | */ |
| 248 | .section .rodata.cortex_a710_regs, "aS" |
| 249 | cortex_a710_regs: /* The ascii list of register names to be reported */ |
| 250 | .asciz "cpuectlr_el1", "" |
| 251 | |
| 252 | func cortex_a710_cpu_reg_dump |
| 253 | adr x6, cortex_a710_regs |
| 254 | mrs x8, CORTEX_A710_CPUECTLR_EL1 |
| 255 | ret |
| 256 | endfunc cortex_a710_cpu_reg_dump |
| 257 | |
| 258 | declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ |
| 259 | cortex_a710_reset_func, \ |
| 260 | cortex_a710_core_pwr_dwn |