blob: ce4239bf613af3ed04188e7246f77d10badbbde1 [file] [log] [blame]
Juan Castillo6b672f52014-09-04 14:43:09 +01001/*
Dan Handley7bef8002015-03-19 19:22:44 +00002 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
Juan Castillo6b672f52014-09-04 14:43:09 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Juan Castillo6b672f52014-09-04 14:43:09 +01005 */
6
Robin Murphy0f1d6662015-01-09 14:30:58 +00007#include <mmio.h>
Vikram Kanigiriaf2bc5f2015-08-03 23:58:19 +01008#include <nic_400.h>
Dan Handley7bef8002015-03-19 19:22:44 +00009#include <plat_arm.h>
10#include <soc_css.h>
Juan Castillo6b672f52014-09-04 14:43:09 +010011#include "juno_def.h"
12
Juan Castillo6b672f52014-09-04 14:43:09 +010013
14/*******************************************************************************
Robin Murphy0f1d6662015-01-09 14:30:58 +000015 * Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
16 * assigned to Non-Secure except some for the DMA-330. Assign those back to the
17 * Non-Secure world as well, otherwise EL1 may end up erroneously generating
18 * (untranslated) Secure transactions if it turns the SMMU on.
19 ******************************************************************************/
20static void init_mmu401(void)
21{
22 uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET);
23 reg |= 0x1FF;
24 mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg);
25}
26
27/*******************************************************************************
Vikram Kanigiriaf2bc5f2015-08-03 23:58:19 +010028 * Program CSS-NIC400 to allow non-secure access to some CSS regions.
29 ******************************************************************************/
30static void css_init_nic400(void)
31{
32 /* Note: This is the NIC-400 device on the CSS */
33 mmio_write_32(PLAT_SOC_CSS_NIC400_BASE +
34 NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE),
35 ~0);
36}
37
38/*******************************************************************************
dp-armb71946b2017-02-08 12:16:42 +000039 * Initialize debug configuration.
40 ******************************************************************************/
41static void init_debug_cfg(void)
42{
43#if !DEBUG
44 /* Set internal drive selection for SPIDEN. */
45 mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET,
46 1U << SPIDEN_SEL_SET_SHIFT);
47
48 /* Drive SPIDEN LOW to disable invasive debug of secure state. */
49 mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
50 1U << SPIDEN_INT_CLR_SHIFT);
51#endif
52}
53
54/*******************************************************************************
Dan Handley7bef8002015-03-19 19:22:44 +000055 * Initialize the secure environment.
Juan Castillo6b672f52014-09-04 14:43:09 +010056 ******************************************************************************/
Dan Handley7bef8002015-03-19 19:22:44 +000057void plat_arm_security_setup(void)
Juan Castillo6b672f52014-09-04 14:43:09 +010058{
dp-armb71946b2017-02-08 12:16:42 +000059 /* Initialize debug configuration */
60 init_debug_cfg();
Juan Castillo6b672f52014-09-04 14:43:09 +010061 /* Initialize the TrustZone Controller */
Soby Mathew9c708b52016-02-26 14:23:19 +000062 arm_tzc400_setup();
Vikram Kanigiriaf2bc5f2015-08-03 23:58:19 +010063 /* Do ARM CSS internal NIC setup */
64 css_init_nic400();
Dan Handley7bef8002015-03-19 19:22:44 +000065 /* Do ARM CSS SoC security setup */
66 soc_css_security_setup();
dp-armb71946b2017-02-08 12:16:42 +000067 /* Initialize the SMMU SSD tables */
Robin Murphy0f1d6662015-01-09 14:30:58 +000068 init_mmu401();
Juan Castillo6b672f52014-09-04 14:43:09 +010069}