Migrate Juno port to use common code
Major update to the Juno platform port to use the common platform code
in (include/)plat/arm/* and (include/)plat/common/*. This mainly
consists of removing duplicated code but also introduces some small
behavioural changes where there was unnecessary variation between the
FVP and Juno ports. See earlier commit titled `Add common ARM and CSS
platform code` for details.
Also move the ARM SoC specific security setup (i.e. NIC-400 and PCIe
initialization) from BL1 to `plat_arm_security_setup()` in BL2,
where the other security setup is done.
Change-Id: Ic9fe01bae8ed382bfb04fc5839a4cfff332eb124
diff --git a/plat/juno/plat_security.c b/plat/juno/plat_security.c
index 254357d..1de38c3 100644
--- a/plat/juno/plat_security.c
+++ b/plat/juno/plat_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,71 +28,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <debug.h>
#include <mmio.h>
-#include <tzc400.h>
+#include <plat_arm.h>
+#include <soc_css.h>
#include "juno_def.h"
-/*******************************************************************************
- * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
- * and allow Non-Secure masters full access
- ******************************************************************************/
-static void init_tzc400(void)
-{
- tzc_init(TZC400_BASE);
-
- /* Disable filters. */
- tzc_disable_filters();
-
- /* Region 1 set to cover Non-Secure DRAM at 0x8000_0000. Apply the
- * same configuration to all filters in the TZC. */
- tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 1,
- DRAM_NS_BASE, DRAM_NS_BASE + DRAM_NS_SIZE - 1,
- TZC_REGION_S_NONE,
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT));
-
- /* Region 2 set to cover Secure DRAM */
- tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 2,
- DRAM_SEC_BASE, DRAM_SEC_BASE + DRAM_SEC_SIZE - 1,
- TZC_REGION_S_RDWR,
- 0);
-
- /* Region 3 set to cover DRAM used by SCP for DDR retraining */
- tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 3,
- DRAM_SCP_BASE, DRAM_SCP_BASE + DRAM_SCP_SIZE - 1,
- TZC_REGION_S_NONE,
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_SCP));
-
- /* Region 4 set to cover Non-Secure DRAM at 0x8_8000_0000 */
- tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 4,
- DRAM2_BASE, DRAM2_BASE + DRAM2_SIZE - 1,
- TZC_REGION_S_NONE,
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT));
-
- /* Raise an exception if a NS device tries to access secure memory */
- tzc_set_action(TZC_ACTION_ERR);
-
- /* Enable filters. */
- tzc_enable_filters();
-}
/*******************************************************************************
* Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
@@ -108,13 +48,14 @@
}
/*******************************************************************************
- * Initialize the secure environment. At this moment only the TrustZone
- * Controller is initialized.
+ * Initialize the secure environment.
******************************************************************************/
-void plat_security_setup(void)
+void plat_arm_security_setup(void)
{
/* Initialize the TrustZone Controller */
- init_tzc400();
+ arm_tzc_setup();
+ /* Do ARM CSS SoC security setup */
+ soc_css_security_setup();
/* Initialize the SMMU SSD tables*/
init_mmu401();
}