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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Ravi Pateleafc8782019-06-21 05:00:49 -07002 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Tejas Patel54d13192019-02-27 18:44:55 +05307#include <assert.h>
8#include <plat_arm.h>
Tejas Patel69409962018-12-14 00:55:29 -08009#include <plat_private.h>
Tejas Patel61717112019-02-27 18:44:57 +053010#include <pm_common.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/debug.h>
12#include <lib/mmio.h>
13#include <lib/psci/psci.h>
14#include <plat/common/platform.h>
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -080015#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016
Tejas Patel61717112019-02-27 18:44:57 +053017#include "pm_api_sys.h"
18#include "pm_client.h"
19
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053020static uintptr_t versal_sec_entry;
21
Tejas Patel61717112019-02-27 18:44:57 +053022static int versal_pwr_domain_on(u_register_t mpidr)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053023{
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053024 unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
Tejas Patel61717112019-02-27 18:44:57 +053025 const struct pm_proc *proc;
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053026
27 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
28
29 if (cpu_id == -1)
30 return PSCI_E_INTERN_FAIL;
31
Tejas Patel61717112019-02-27 18:44:57 +053032 proc = pm_get_proc(cpu_id);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053033
Tejas Patel61717112019-02-27 18:44:57 +053034 /* Send request to PMC to wake up selected ACPU core */
35 pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFF) | 0x1,
Tejas Patel18072da2021-02-25 20:16:56 -080036 versal_sec_entry >> 32, 0, SECURE_FLAG);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053037
Tejas Patel61717112019-02-27 18:44:57 +053038 /* Clear power down request */
39 pm_client_wakeup(proc);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053040
41 return PSCI_E_SUCCESS;
42}
43
Tejas Patel54d13192019-02-27 18:44:55 +053044/**
45 * versal_pwr_domain_suspend() - This function sends request to PMC to suspend
46 * core.
47 *
48 * @target_state Targated state
49 */
50static void versal_pwr_domain_suspend(const psci_power_state_t *target_state)
51{
52 unsigned int state;
53 unsigned int cpu_id = plat_my_core_pos();
54 const struct pm_proc *proc = pm_get_proc(cpu_id);
55
56 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
57 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
58 __func__, i, target_state->pwr_domain_state[i]);
59
60 plat_versal_gic_cpuif_disable();
61
Ravi Pateleafc8782019-06-21 05:00:49 -070062 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
63 plat_versal_gic_save();
64 }
Tejas Patel54d13192019-02-27 18:44:55 +053065
66 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
67 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
68
69 /* Send request to PMC to suspend this core */
Tejas Patel18072da2021-02-25 20:16:56 -080070 pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry,
71 SECURE_FLAG);
Tejas Patel54d13192019-02-27 18:44:55 +053072
73 /* APU is to be turned off */
74 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
75 /* disable coherency */
76 plat_arm_interconnect_exit_coherency();
77 }
78}
79
80/**
81 * versal_pwr_domain_suspend_finish() - This function performs actions to finish
82 * suspend procedure.
83 *
84 * @target_state Targated state
85 */
86static void versal_pwr_domain_suspend_finish(
87 const psci_power_state_t *target_state)
88{
89 unsigned int cpu_id = plat_my_core_pos();
90 const struct pm_proc *proc = pm_get_proc(cpu_id);
91
92 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
93 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
94 __func__, i, target_state->pwr_domain_state[i]);
95
96 /* Clear the APU power control register for this cpu */
97 pm_client_wakeup(proc);
98
99 /* enable coherency */
100 plat_arm_interconnect_enter_coherency();
101
102 /* APU was turned off, so restore GIC context */
103 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
104 plat_versal_gic_resume();
Tejas Patel54d13192019-02-27 18:44:55 +0530105 }
Ravi Pateleafc8782019-06-21 05:00:49 -0700106
107 plat_versal_gic_cpuif_enable();
Tejas Patel54d13192019-02-27 18:44:55 +0530108}
109
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530110void versal_pwr_domain_on_finish(const psci_power_state_t *target_state)
111{
112 /* Enable the gic cpu interface */
113 plat_versal_gic_pcpu_init();
114
115 /* Program the gic per-cpu distributor or re-distributor interface */
116 plat_versal_gic_cpuif_enable();
117}
118
Tejas Patel54d13192019-02-27 18:44:55 +0530119/**
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800120 * versal_system_off() - This function sends the system off request
121 * to firmware. This function does not return.
122 */
123static void __dead2 versal_system_off(void)
124{
125 /* Send the power down request to the PMC */
126 pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
Tejas Patel18072da2021-02-25 20:16:56 -0800127 pm_get_shutdown_scope(), SECURE_FLAG);
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800128
129 while (1)
130 wfi();
131}
132
133/**
134 * versal_system_reset() - This function sends the reset request
135 * to firmware for the system to reset. This function does not return.
136 */
137static void __dead2 versal_system_reset(void)
138{
139 /* Send the system reset request to the PMC */
140 pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
Tejas Patel18072da2021-02-25 20:16:56 -0800141 pm_get_shutdown_scope(), SECURE_FLAG);
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800142
143 while (1)
144 wfi();
145}
146
147/**
Tejas Patel54d13192019-02-27 18:44:55 +0530148 * versal_pwr_domain_off() - This function performs actions to turn off core
149 *
150 * @target_state Targated state
151 */
152static void versal_pwr_domain_off(const psci_power_state_t *target_state)
153{
154 unsigned int cpu_id = plat_my_core_pos();
155 const struct pm_proc *proc = pm_get_proc(cpu_id);
156
157 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
158 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
159 __func__, i, target_state->pwr_domain_state[i]);
160
161 /* Prevent interrupts from spuriously waking up this cpu */
162 plat_versal_gic_cpuif_disable();
163
164 /*
165 * Send request to PMC to power down the appropriate APU CPU
166 * core.
167 * According to PSCI specification, CPU_off function does not
168 * have resume address and CPU core can only be woken up
169 * invoking CPU_on function, during which resume address will
170 * be set.
171 */
Tejas Patel18072da2021-02-25 20:16:56 -0800172 pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0,
173 SECURE_FLAG);
Tejas Patel54d13192019-02-27 18:44:55 +0530174}
175
176/**
177 * versal_validate_power_state() - This function ensures that the power state
178 * parameter in request is valid.
179 *
180 * @power_state Power state of core
181 * @req_state Requested state
182 *
183 * @return Returns status, either success or reason
184 */
185static int versal_validate_power_state(unsigned int power_state,
186 psci_power_state_t *req_state)
187{
188 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
189
190 int pstate = psci_get_pstate_type(power_state);
191
192 assert(req_state);
193
194 /* Sanity check the requested state */
195 if (pstate == PSTATE_TYPE_STANDBY)
196 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
197 else
198 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
199
200 /* We expect the 'state id' to be zero */
201 if (psci_get_pstate_id(power_state))
202 return PSCI_E_INVALID_PARAMS;
203
204 return PSCI_E_SUCCESS;
205}
206
207/**
208 * versal_get_sys_suspend_power_state() - Get power state for system suspend
209 *
210 * @req_state Requested state
211 */
212static void versal_get_sys_suspend_power_state(psci_power_state_t *req_state)
213{
214 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
215 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
216}
217
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530218static const struct plat_psci_ops versal_nopmc_psci_ops = {
Tejas Patel61717112019-02-27 18:44:57 +0530219 .pwr_domain_on = versal_pwr_domain_on,
Tejas Patel54d13192019-02-27 18:44:55 +0530220 .pwr_domain_off = versal_pwr_domain_off,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530221 .pwr_domain_on_finish = versal_pwr_domain_on_finish,
Tejas Patel54d13192019-02-27 18:44:55 +0530222 .pwr_domain_suspend = versal_pwr_domain_suspend,
223 .pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish,
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800224 .system_off = versal_system_off,
225 .system_reset = versal_system_reset,
Tejas Patel54d13192019-02-27 18:44:55 +0530226 .validate_power_state = versal_validate_power_state,
227 .get_sys_suspend_power_state = versal_get_sys_suspend_power_state,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530228};
229
230/*******************************************************************************
231 * Export the platform specific power ops.
232 ******************************************************************************/
233int plat_setup_psci_ops(uintptr_t sec_entrypoint,
234 const struct plat_psci_ops **psci_ops)
235{
236 versal_sec_entry = sec_entrypoint;
237
238 *psci_ops = &versal_nopmc_psci_ops;
239
240 return 0;
241}