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git01.mediatek.com / filogic / atf / 94e197668ce3d4314e692e9c061a4b05efd1a2ba / . / bl2 / aarch32 / bl2_el3_entrypoint.S
blob: 7e855516d497e9ef34954d3b5f3f8d5947c17c9f [file] [log] [blame]
Roberto Vargase0e99462017-10-30 14:43:43 +0000[diff] [blame]1/*
Yann Gautier514e59c2020-10-05 11:02:54 +0200[diff] [blame]2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
Roberto Vargase0e99462017-10-30 14:43:43 +0000[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]9#include <common/bl_common.h>
Roberto Vargase0e99462017-10-30 14:43:43 +0000[diff] [blame]10#include <el3_common_macros.S>
11
Roberto Vargase0e99462017-10-30 14:43:43 +0000[diff] [blame]12 .globl bl2_entrypoint
13 .globl bl2_run_next_image
14
15
16func bl2_entrypoint
17 /* Save arguments x0-x3 from previous Boot loader */
18 mov r9, r0
19 mov r10, r1
20 mov r11, r2
21 mov r12, r3
22
23 el3_entrypoint_common \
24 _init_sctlr=1 \
25 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
26 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
27 _init_memory=1 \
28 _init_c_runtime=1 \
Yann Gautier514e59c2020-10-05 11:02:54 +0200[diff] [blame]29 _exception_vectors=bl2_vector_table \
30 _pie_fixup_size=0
Roberto Vargase0e99462017-10-30 14:43:43 +0000[diff] [blame]31
32 /*
33 * Restore parameters of boot rom
34 */
35 mov r0, r9
36 mov r1, r10
37 mov r2, r11
38 mov r3, r12
39
Antonio Nino Diaz4f29fb72019-01-31 17:40:44 +0000[diff] [blame]40 /* ---------------------------------------------
41 * Perform BL2 setup
42 * ---------------------------------------------
43 */
44 bl bl2_el3_setup
Roberto Vargase0e99462017-10-30 14:43:43 +0000[diff] [blame]45
46 /* ---------------------------------------------
47 * Jump to main function.
48 * ---------------------------------------------
49 */
50 bl bl2_main
51
52 /* ---------------------------------------------
53 * Should never reach this point.
54 * ---------------------------------------------
55 */
56 no_ret plat_panic_handler
57
58endfunc bl2_entrypoint
59
60func bl2_run_next_image
61 mov r8,r0
62
63 /*
64 * MMU needs to be disabled because both BL2 and BL32 execute
65 * in PL1, and therefore share the same address space.
66 * BL32 will initialize the address space according to its
67 * own requirement.
68 */
69 bl disable_mmu_icache_secure
70 stcopr r0, TLBIALL
71 dsb sy
72 isb
73 mov r0, r8
74 bl bl2_el3_plat_prepare_exit
75
76 /*
77 * Extract PC and SPSR based on struct `entry_point_info_t`
78 * and load it in LR and SPSR registers respectively.
79 */
80 ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
81 ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
Bryan O'Donoghue033186c2019-03-11 15:36:07 +0000[diff] [blame]82 msr spsr_xc, r1
Roberto Vargase0e99462017-10-30 14:43:43 +0000[diff] [blame]83
Lionel Debieve6a897542018-03-05 15:21:59 +0100[diff] [blame]84 /* Some BL32 stages expect lr_svc to provide the BL33 entry address */
85 cps #MODE32_svc
86 ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET]
87 cps #MODE32_mon
88
Roberto Vargase0e99462017-10-30 14:43:43 +0000[diff] [blame]89 add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
90 ldm r8, {r0, r1, r2, r3}
Madhukar Pappireddyfcbcd6f2020-02-26 12:37:05 -0600[diff] [blame]91 exception_return
Roberto Vargase0e99462017-10-30 14:43:43 +0000[diff] [blame]92endfunc bl2_run_next_image