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git01.mediatek.com / filogic / atf / 9490f1f26b11c098e20ddbcafc1209169356ec9b / . / include / plat / arm / board / common / board_css_def.h
blob: 3bb68ee35669901f24910fb6a0a18273eb07f8b5 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]1/*
Manish V Badarkhedd6f2522021-02-22 17:30:17 +0000[diff] [blame]2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef BOARD_CSS_DEF_H
8#define BOARD_CSS_DEF_H
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10#include <lib/utils_def.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +0000[diff] [blame]11#include <plat/arm/board/common/v2m_def.h>
12#include <plat/arm/soc/common/soc_css_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]13#include <plat/common/common_def.h>
14
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]15/*
16 * Definitions common to all ARM CSS-based development platforms
17 */
18
19/* Platform ID address */
20#define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0
21
22/* Platform ID related accessors */
23#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f
24#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0
25#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00
26#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8
27#define BOARD_CSS_PLAT_TYPE_RTL 0x00
28#define BOARD_CSS_PLAT_TYPE_FPGA 0x01
29#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
30#define BOARD_CSS_PLAT_TYPE_FVP 0x03
31
Julius Werner53456fc2019-07-09 13:49:11 -0700[diff] [blame]32#ifndef __ASSEMBLER__
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]33
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]34#include <lib/mmio.h>
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]35
36#define BOARD_CSS_GET_PLAT_TYPE(addr) \
37 ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
38 >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
39
Julius Werner53456fc2019-07-09 13:49:11 -0700[diff] [blame]40#endif /* __ASSEMBLER__ */
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]41
42
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100[diff] [blame]43#define MAX_IO_DEVICES 3
44#define MAX_IO_HANDLES 4
45
46/* Reserve the last block of flash for PSCI MEM PROTECT flag */
Manish V Badarkhe443ccbc2021-04-22 11:13:21 +0100[diff] [blame]47#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
48#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100[diff] [blame]49
Manish V Badarkhedd6f2522021-02-22 17:30:17 +0000[diff] [blame]50#if ARM_GPT_SUPPORT
51/*
52 * Offset of the FIP in the GPT image. BL1 component uses this option
53 * as it does not load the partition table to get the FIP base
54 * address. At sector 34 by default (i.e. after reserved sectors 0-33)
55 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
56 */
57#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400
58#endif /* ARM_GPT_SUPPORT */
59
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100[diff] [blame]60#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
61#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
62
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]63/* UART related constants */
64#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
65#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
66
Usama Arif81eb5ce2019-02-11 16:35:42 +0000[diff] [blame]67#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE
68#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
Soby Mathew2fd66be2015-12-09 11:38:43 +0000[diff] [blame]69
Usama Arif81eb5ce2019-02-11 16:35:42 +0000[diff] [blame]70#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
71#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]72
73#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE
74#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
75
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]76#endif /* BOARD_CSS_DEF_H */