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Olivier Deprezbe671112019-10-28 09:07:50 +00001/*
Daniel Boulby9460a232021-12-09 11:20:13 +00002 * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
Olivier Deprezbe671112019-10-28 09:07:50 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
Olivier Deprez33e44122020-04-16 17:54:27 +02008#include <errno.h>
Scott Brandene5dcf982020-08-25 13:49:32 -07009#include <inttypes.h>
10#include <stdint.h>
11
Olivier Deprezc7631a52020-03-23 09:53:06 +010012#include <lib/el3_runtime/context_mgmt.h>
Olivier Depreze799f482021-03-02 17:31:22 +010013#include <lib/spinlock.h>
Olivier Deprezbe671112019-10-28 09:07:50 +000014#include "spmd_private.h"
15
Olivier Deprezeae45962021-01-19 15:06:47 +010016static struct {
17 bool secondary_ep_locked;
18 uintptr_t secondary_ep;
Olivier Depreze799f482021-03-02 17:31:22 +010019 spinlock_t lock;
Olivier Deprezeae45962021-01-19 15:06:47 +010020} g_spmd_pm;
21
Olivier Deprez33e44122020-04-16 17:54:27 +020022/*******************************************************************************
Olivier Deprezeae45962021-01-19 15:06:47 +010023 * spmd_pm_secondary_ep_register
Olivier Deprez33e44122020-04-16 17:54:27 +020024 ******************************************************************************/
Olivier Deprezeae45962021-01-19 15:06:47 +010025int spmd_pm_secondary_ep_register(uintptr_t entry_point)
Olivier Deprez33e44122020-04-16 17:54:27 +020026{
Olivier Depreze799f482021-03-02 17:31:22 +010027 int ret = FFA_ERROR_INVALID_PARAMETER;
28
29 spin_lock(&g_spmd_pm.lock);
30
Olivier Deprezeae45962021-01-19 15:06:47 +010031 if (g_spmd_pm.secondary_ep_locked == true) {
Olivier Depreze799f482021-03-02 17:31:22 +010032 goto out;
Olivier Deprez33e44122020-04-16 17:54:27 +020033 }
34
Olivier Deprez33e44122020-04-16 17:54:27 +020035 /*
36 * Check entry_point address is a PA within
37 * load_address <= entry_point < load_address + binary_size
38 */
39 if (!spmd_check_address_in_binary_image(entry_point)) {
Olivier Deprezeae45962021-01-19 15:06:47 +010040 ERROR("%s entry point is not within image boundaries\n",
41 __func__);
Olivier Depreze799f482021-03-02 17:31:22 +010042 goto out;
Olivier Deprez33e44122020-04-16 17:54:27 +020043 }
44
Olivier Deprezeae45962021-01-19 15:06:47 +010045 g_spmd_pm.secondary_ep = entry_point;
46 g_spmd_pm.secondary_ep_locked = true;
Olivier Deprez73ef0dc2020-06-19 15:33:41 +020047
Olivier Deprezeae45962021-01-19 15:06:47 +010048 VERBOSE("%s %lx\n", __func__, entry_point);
Olivier Deprez33e44122020-04-16 17:54:27 +020049
Olivier Depreze799f482021-03-02 17:31:22 +010050 ret = 0;
51
52out:
53 spin_unlock(&g_spmd_pm.lock);
54
55 return ret;
Olivier Deprez33e44122020-04-16 17:54:27 +020056}
57
Olivier Deprezbe671112019-10-28 09:07:50 +000058/*******************************************************************************
59 * This CPU has been turned on. Enter SPMC to initialise S-EL1 or S-EL2. As part
60 * of the SPMC initialization path, they will initialize any SPs that they
61 * manage. Entry into SPMC is done after initialising minimal architectural
62 * state that guarantees safe execution.
63 ******************************************************************************/
64static void spmd_cpu_on_finish_handler(u_register_t unused)
65{
Olivier Deprezbe671112019-10-28 09:07:50 +000066 spmd_spm_core_context_t *ctx = spmd_get_context();
Olivier Deprezc7631a52020-03-23 09:53:06 +010067 unsigned int linear_id = plat_my_core_pos();
Olivier Deprez4ab7a4a2021-06-21 09:47:13 +020068 el3_state_t *el3_state;
69 uintptr_t entry_point;
Olivier Deprez73ef0dc2020-06-19 15:33:41 +020070 uint64_t rc;
Olivier Deprezbe671112019-10-28 09:07:50 +000071
Olivier Deprezc7631a52020-03-23 09:53:06 +010072 assert(ctx != NULL);
Olivier Deprezbe671112019-10-28 09:07:50 +000073 assert(ctx->state != SPMC_STATE_ON);
Olivier Deprezc7631a52020-03-23 09:53:06 +010074
Olivier Depreze799f482021-03-02 17:31:22 +010075 spin_lock(&g_spmd_pm.lock);
76
Olivier Deprezc7631a52020-03-23 09:53:06 +010077 /*
Olivier Deprezeae45962021-01-19 15:06:47 +010078 * Leave the possibility that the SPMC does not call
79 * FFA_SECONDARY_EP_REGISTER in which case re-use the
80 * primary core address for booting secondary cores.
Olivier Deprezc7631a52020-03-23 09:53:06 +010081 */
Olivier Deprezeae45962021-01-19 15:06:47 +010082 if (g_spmd_pm.secondary_ep_locked == true) {
Olivier Deprez4ab7a4a2021-06-21 09:47:13 +020083 /*
84 * The CPU context has already been initialized at boot time
85 * (in spmd_spmc_init by a call to cm_setup_context). Adjust
86 * below the target core entry point based on the address
87 * passed to by FFA_SECONDARY_EP_REGISTER.
88 */
89 entry_point = g_spmd_pm.secondary_ep;
90 el3_state = get_el3state_ctx(&ctx->cpu_ctx);
91 write_ctx_reg(el3_state, CTX_ELR_EL3, entry_point);
Olivier Deprezc7631a52020-03-23 09:53:06 +010092 }
93
Olivier Depreze799f482021-03-02 17:31:22 +010094 spin_unlock(&g_spmd_pm.lock);
95
Olivier Deprez4ab7a4a2021-06-21 09:47:13 +020096 /* Mark CPU as initiating ON operation. */
Olivier Deprezc7631a52020-03-23 09:53:06 +010097 ctx->state = SPMC_STATE_ON_PENDING;
Olivier Deprezbe671112019-10-28 09:07:50 +000098
99 rc = spmd_spm_core_sync_entry(ctx);
Olivier Deprez73ef0dc2020-06-19 15:33:41 +0200100 if (rc != 0ULL) {
Scott Brandene5dcf982020-08-25 13:49:32 -0700101 ERROR("%s failed (%" PRIu64 ") on CPU%u\n", __func__, rc,
Olivier Deprezc7631a52020-03-23 09:53:06 +0100102 linear_id);
Olivier Deprezbe671112019-10-28 09:07:50 +0000103 ctx->state = SPMC_STATE_OFF;
104 return;
105 }
106
107 ctx->state = SPMC_STATE_ON;
Olivier Deprezc7631a52020-03-23 09:53:06 +0100108
109 VERBOSE("CPU %u on!\n", linear_id);
110}
111
112/*******************************************************************************
113 * spmd_cpu_off_handler
114 ******************************************************************************/
115static int32_t spmd_cpu_off_handler(u_register_t unused)
116{
117 spmd_spm_core_context_t *ctx = spmd_get_context();
118 unsigned int linear_id = plat_my_core_pos();
Olivier Deprez73ef0dc2020-06-19 15:33:41 +0200119 int64_t rc;
Olivier Deprezc7631a52020-03-23 09:53:06 +0100120
121 assert(ctx != NULL);
122 assert(ctx->state != SPMC_STATE_OFF);
123
Olivier Deprezc7631a52020-03-23 09:53:06 +0100124 /* Build an SPMD to SPMC direct message request. */
Daniel Boulby9460a232021-12-09 11:20:13 +0000125 spmd_build_spmc_message(get_gpregs_ctx(&ctx->cpu_ctx),
126 SPMD_FWK_MSG_PSCI, PSCI_CPU_OFF);
Olivier Deprezc7631a52020-03-23 09:53:06 +0100127
128 rc = spmd_spm_core_sync_entry(ctx);
Olivier Deprez73ef0dc2020-06-19 15:33:41 +0200129 if (rc != 0ULL) {
Scott Brandene5dcf982020-08-25 13:49:32 -0700130 ERROR("%s failed (%" PRIu64 ") on CPU%u\n", __func__, rc, linear_id);
Olivier Deprezc7631a52020-03-23 09:53:06 +0100131 }
132
Olivier Deprezeae45962021-01-19 15:06:47 +0100133 /* Expect a direct message response from the SPMC. */
134 u_register_t ffa_resp_func = read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx),
135 CTX_GPREG_X0);
136 if (ffa_resp_func != FFA_MSG_SEND_DIRECT_RESP_SMC32) {
137 ERROR("%s invalid SPMC response (%lx).\n",
138 __func__, ffa_resp_func);
139 return -EINVAL;
140 }
Olivier Deprezc7631a52020-03-23 09:53:06 +0100141
Olivier Deprezc7631a52020-03-23 09:53:06 +0100142 ctx->state = SPMC_STATE_OFF;
143
144 VERBOSE("CPU %u off!\n", linear_id);
145
146 return 0;
Olivier Deprezbe671112019-10-28 09:07:50 +0000147}
148
149/*******************************************************************************
150 * Structure populated by the SPM Dispatcher to perform any bookkeeping before
151 * PSCI executes a power mgmt. operation.
152 ******************************************************************************/
153const spd_pm_ops_t spmd_pm = {
154 .svc_on_finish = spmd_cpu_on_finish_handler,
Olivier Deprezc7631a52020-03-23 09:53:06 +0100155 .svc_off = spmd_cpu_off_handler
Olivier Deprezbe671112019-10-28 09:07:50 +0000156};