blob: eff59adb1615433dcfbe322ab14299bdc606890a [file] [log] [blame]
Olivier Deprezbe671112019-10-28 09:07:50 +00001/*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include "spmd_private.h"
9
10/*******************************************************************************
11 * This CPU has been turned on. Enter SPMC to initialise S-EL1 or S-EL2. As part
12 * of the SPMC initialization path, they will initialize any SPs that they
13 * manage. Entry into SPMC is done after initialising minimal architectural
14 * state that guarantees safe execution.
15 ******************************************************************************/
16static void spmd_cpu_on_finish_handler(u_register_t unused)
17{
18 unsigned int linear_id = plat_my_core_pos();
19 spmd_spm_core_context_t *ctx = spmd_get_context();
20 int rc;
21
22 assert(ctx->state != SPMC_STATE_ON);
23
24 rc = spmd_spm_core_sync_entry(ctx);
25 if (rc != 0) {
26 ERROR("SPMC initialisation failed (%d) on CPU%u\n", rc,
27 linear_id);
28 ctx->state = SPMC_STATE_OFF;
29 return;
30 }
31
32 ctx->state = SPMC_STATE_ON;
33}
34
35/*******************************************************************************
36 * Structure populated by the SPM Dispatcher to perform any bookkeeping before
37 * PSCI executes a power mgmt. operation.
38 ******************************************************************************/
39const spd_pm_ops_t spmd_pm = {
40 .svc_on_finish = spmd_cpu_on_finish_handler,
41};