Soby Mathew | 5f6412a | 2018-02-08 11:39:38 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
| 9 | / { |
| 10 | /* Platform Config */ |
| 11 | plat_arm_bl2 { |
| 12 | compatible = "arm,tb_fw"; |
| 13 | hw_config_addr = <0x0 0x82000000>; |
| 14 | hw_config_max_size = <0x01000000>; |
Soby Mathew | 45e39e2 | 2018-03-26 15:16:46 +0100 | [diff] [blame] | 15 | /* Disable authentication for development */ |
Daniel Boulby | d02000d | 2018-06-22 16:44:57 +0100 | [diff] [blame] | 16 | disable_auth = <0x0>; |
Soby Mathew | b681484 | 2018-04-04 09:40:32 +0100 | [diff] [blame] | 17 | /* |
| 18 | * Load SoC and TOS firmware configs at the base of |
| 19 | * non shared SRAM. The runtime checks ensure we don't |
| 20 | * overlap BL2, BL31 or BL32. The NT firmware config |
| 21 | * is loaded at base of DRAM. |
| 22 | */ |
| 23 | soc_fw_config_addr = <0x0 0x04001000>; |
| 24 | soc_fw_config_max_size = <0x200>; |
| 25 | tos_fw_config_addr = <0x0 0x04001200>; |
| 26 | tos_fw_config_max_size = <0x200>; |
| 27 | nt_fw_config_addr = <0x0 0x80000000>; |
| 28 | nt_fw_config_max_size = <0x200>; |
Soby Mathew | 5f6412a | 2018-02-08 11:39:38 +0000 | [diff] [blame] | 29 | }; |
| 30 | }; |