blob: 0430048e21e17fb9ed8afb0e548ee9b902dd0392 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Varun Wadekar84a775e2019-01-03 10:12:55 -08002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb5b15b22018-05-17 10:10:25 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05306 */
7
Varun Wadekarb316e242015-05-19 16:48:04 +05308#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <platform_def.h>
11
12#include <arch_helpers.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053015#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <drivers/console.h>
17#include <lib/el3_runtime/context_mgmt.h>
18#include <lib/mmio.h>
19#include <lib/psci/psci.h>
20#include <plat/common/platform.h>
21
Varun Wadekarb316e242015-05-19 16:48:04 +053022#include <memctrl.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053023#include <pmc.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053024#include <tegra_def.h>
Harvey Hsieh9e083c72017-04-10 16:20:32 +080025#include <tegra_platform.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053026#include <tegra_private.h>
27
28extern uint64_t tegra_bl31_phys_base;
Varun Wadekara78bb1b2015-08-07 10:03:00 +053029extern uint64_t tegra_sec_entry_point;
Varun Wadekarb316e242015-05-19 16:48:04 +053030
Varun Wadekarb316e242015-05-19 16:48:04 +053031/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +053032 * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
33 * call to get the `power_state` parameter. This allows the platform to encode
34 * the appropriate State-ID field within the `power_state` parameter which can
35 * be utilized in `pwr_domain_suspend()` to suspend to system affinity level.
36******************************************************************************/
37void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053038{
Varun Wadekarf2aa1be2016-06-07 12:00:06 -070039 /* all affinities use system suspend state id */
Anthony Zhou85a8fa02017-03-22 14:42:42 +080040 for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) {
Varun Wadekarf2aa1be2016-06-07 12:00:06 -070041 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN;
Anthony Zhou85a8fa02017-03-22 14:42:42 +080042 }
Varun Wadekarb316e242015-05-19 16:48:04 +053043}
44
45/*******************************************************************************
46 * Handler called when an affinity instance is about to enter standby.
47 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +053048void tegra_cpu_standby(plat_local_state_t cpu_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053049{
Vignesh Radhakrishnan16d82ae2018-04-20 14:31:41 -070050 u_register_t saved_scr_el3;
51
Anthony Zhou85a8fa02017-03-22 14:42:42 +080052 (void)cpu_state;
53
Varun Wadekarb3421ce2017-12-27 18:10:12 -080054 /* Tegra SoC specific handler */
55 if (tegra_soc_cpu_standby(cpu_state) != PSCI_E_SUCCESS)
56 ERROR("%s failed\n", __func__);
57
Vignesh Radhakrishnan16d82ae2018-04-20 14:31:41 -070058 saved_scr_el3 = read_scr_el3();
59
60 /*
61 * As per ARM ARM D1.17.2, any physical IRQ interrupt received by the
62 * PE will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1',
63 * irrespective of the value of the PSTATE.I bit value.
64 */
65 write_scr_el3(saved_scr_el3 | SCR_IRQ_BIT);
66
Varun Wadekarb316e242015-05-19 16:48:04 +053067 /*
68 * Enter standby state
Vignesh Radhakrishnan16d82ae2018-04-20 14:31:41 -070069 *
70 * dsb & isb is good practice before using wfi to enter low power states
Varun Wadekarb316e242015-05-19 16:48:04 +053071 */
72 dsb();
Vignesh Radhakrishnan16d82ae2018-04-20 14:31:41 -070073 isb();
Varun Wadekarb316e242015-05-19 16:48:04 +053074 wfi();
Vignesh Radhakrishnan16d82ae2018-04-20 14:31:41 -070075
76 /*
77 * Restore saved scr_el3 that has IRQ bit cleared as we don't want EL3
78 * handling any further interrupts
79 */
80 write_scr_el3(saved_scr_el3);
Varun Wadekarb316e242015-05-19 16:48:04 +053081}
82
83/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +053084 * Handler called when an affinity instance is about to be turned on. The
85 * level and mpidr determine the affinity instance.
86 ******************************************************************************/
Anthony Zhou85a8fa02017-03-22 14:42:42 +080087int32_t tegra_pwr_domain_on(u_register_t mpidr)
Varun Wadekarb316e242015-05-19 16:48:04 +053088{
Varun Wadekara78bb1b2015-08-07 10:03:00 +053089 return tegra_soc_pwr_domain_on(mpidr);
Varun Wadekarb316e242015-05-19 16:48:04 +053090}
91
92/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +053093 * Handler called when a power domain is about to be turned off. The
94 * target_state encodes the power state that each level should transition to.
Varun Wadekarb316e242015-05-19 16:48:04 +053095 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +053096void tegra_pwr_domain_off(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053097{
Anthony Zhou85a8fa02017-03-22 14:42:42 +080098 (void)tegra_soc_pwr_domain_off(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +053099}
100
101/*******************************************************************************
Varun Wadekard22429d2016-03-18 14:35:28 -0700102 * Handler called when a power domain is about to be suspended. The
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530103 * target_state encodes the power state that each level should transition to.
Varun Wadekar99782e82017-07-05 17:44:12 -0700104 * This handler is called with SMP and data cache enabled, when
105 * HW_ASSISTED_COHERENCY = 0
106 ******************************************************************************/
107void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
108{
109 tegra_soc_pwr_domain_suspend_pwrdown_early(target_state);
110}
111
112/*******************************************************************************
113 * Handler called when a power domain is about to be suspended. The
114 * target_state encodes the power state that each level should transition to.
Varun Wadekarb316e242015-05-19 16:48:04 +0530115 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530116void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530117{
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800118 (void)tegra_soc_pwr_domain_suspend(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530119
Varun Wadekara2c6be62016-08-01 22:16:21 -0700120 /* Disable console if we are entering deep sleep. */
121 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800122 PSTATE_ID_SOC_POWERDN) {
Ambroise Vincent09a22e72019-05-29 14:04:16 +0100123 (void)console_flush();
124 console_switch_state(0);
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800125 }
Varun Wadekara2c6be62016-08-01 22:16:21 -0700126
Varun Wadekarb316e242015-05-19 16:48:04 +0530127 /* disable GICC */
128 tegra_gic_cpuif_deactivate();
129}
130
131/*******************************************************************************
Varun Wadekard22429d2016-03-18 14:35:28 -0700132 * Handler called at the end of the power domain suspend sequence. The
133 * target_state encodes the power state that each level should transition to.
134 ******************************************************************************/
135__dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
136 *target_state)
137{
138 /* call the chip's power down handler */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800139 (void)tegra_soc_pwr_domain_power_down_wfi(target_state);
Varun Wadekard22429d2016-03-18 14:35:28 -0700140
Vignesh Radhakrishnan833d89c2017-05-25 10:31:42 -0700141 wfi();
Varun Wadekard22429d2016-03-18 14:35:28 -0700142 panic();
143}
144
145/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530146 * Handler called when a power domain has just been powered on after
147 * being turned off earlier. The target_state encodes the low power state that
148 * each level has woken up from.
Varun Wadekarb316e242015-05-19 16:48:04 +0530149 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530150void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530151{
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800152 const plat_params_from_bl2_t *plat_params;
Varun Wadekarb316e242015-05-19 16:48:04 +0530153
154 /*
Varun Wadekarb316e242015-05-19 16:48:04 +0530155 * Check if we are exiting from deep sleep.
156 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530157 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
158 PSTATE_ID_SOC_POWERDN) {
Varun Wadekarb316e242015-05-19 16:48:04 +0530159
Varun Wadekarfd60a272020-03-21 18:49:33 -0700160 /*
161 * On entering System Suspend state, the GIC loses power
162 * completely. Initialize the GIC global distributor and
163 * GIC cpu interfaces.
164 */
165 tegra_gic_init();
166
Ambroise Vincent09a22e72019-05-29 14:04:16 +0100167 /* Restart console output. */
168 console_switch_state(CONSOLE_FLAG_RUNTIME);
Varun Wadekara2c6be62016-08-01 22:16:21 -0700169
Varun Wadekarb316e242015-05-19 16:48:04 +0530170 /*
Varun Wadekar6eec6d62016-03-03 13:28:10 -0800171 * Restore Memory Controller settings as it loses state
172 * during system suspend.
Varun Wadekarb316e242015-05-19 16:48:04 +0530173 */
Varun Wadekar6eec6d62016-03-03 13:28:10 -0800174 tegra_memctrl_restore_settings();
Varun Wadekarb316e242015-05-19 16:48:04 +0530175
176 /*
177 * Security configuration to allow DRAM/device access.
178 */
179 plat_params = bl31_get_plat_params();
Varun Wadekar6bb62462015-10-06 12:49:31 +0530180 tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800181 (uint32_t)plat_params->tzdram_size);
Varun Wadekard5f578a2016-06-01 19:34:37 -0700182
183 /*
184 * Set up the TZRAM memory aperture to allow only secure world
185 * access
186 */
187 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
Varun Wadekarfd60a272020-03-21 18:49:33 -0700188 } else {
189 /*
190 * Initialize the GIC cpu and distributor interfaces
191 */
192 tegra_gic_pcpu_init();
Varun Wadekarb316e242015-05-19 16:48:04 +0530193 }
194
195 /*
196 * Reset hardware settings.
197 */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800198 (void)tegra_soc_pwr_domain_on_finish(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530199}
200
201/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530202 * Handler called when a power domain has just been powered on after
203 * having been suspended earlier. The target_state encodes the low power state
204 * that each level has woken up from.
Varun Wadekarb316e242015-05-19 16:48:04 +0530205 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530206void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530207{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530208 tegra_pwr_domain_on_finish(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530209}
210
211/*******************************************************************************
212 * Handler called when the system wants to be powered off
213 ******************************************************************************/
214__dead2 void tegra_system_off(void)
215{
Varun Wadekare5caeed2016-01-07 14:04:21 -0800216 INFO("Powering down system...\n");
217
218 tegra_soc_prepare_system_off();
Varun Wadekarb316e242015-05-19 16:48:04 +0530219}
220
221/*******************************************************************************
222 * Handler called when the system wants to be restarted.
223 ******************************************************************************/
224__dead2 void tegra_system_reset(void)
225{
Varun Wadekare5caeed2016-01-07 14:04:21 -0800226 INFO("Restarting system...\n");
227
Varun Wadekar8b82fae2015-11-09 17:39:28 -0800228 /* per-SoC system reset handler */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800229 (void)tegra_soc_prepare_system_reset();
Varun Wadekar8b82fae2015-11-09 17:39:28 -0800230
Varun Wadekar29b46652018-05-17 11:10:13 -0700231 /* wait for the system to reset */
232 for (;;) {
233 ;
234 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530235}
236
237/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530238 * Handler called to check the validity of the power state parameter.
239 ******************************************************************************/
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800240int32_t tegra_validate_power_state(uint32_t power_state,
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530241 psci_power_state_t *req_state)
242{
Anthony Zhou4408e882017-07-07 14:29:51 +0800243 assert(req_state != NULL);
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530244
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530245 return tegra_soc_validate_power_state(power_state, req_state);
246}
247
248/*******************************************************************************
249 * Platform handler called to check the validity of the non secure entrypoint.
250 ******************************************************************************/
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800251int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint)
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530252{
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800253 int32_t ret = PSCI_E_INVALID_ADDRESS;
254
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530255 /*
256 * Check if the non secure entrypoint lies within the non
257 * secure DRAM.
258 */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800259 if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) {
260 ret = PSCI_E_SUCCESS;
261 }
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530262
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800263 return ret;
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530264}
265
266/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530267 * Export the platform handlers to enable psci to invoke them
268 ******************************************************************************/
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700269static plat_psci_ops_t tegra_plat_psci_ops = {
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530270 .cpu_standby = tegra_cpu_standby,
271 .pwr_domain_on = tegra_pwr_domain_on,
272 .pwr_domain_off = tegra_pwr_domain_off,
Varun Wadekar99782e82017-07-05 17:44:12 -0700273 .pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early,
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530274 .pwr_domain_suspend = tegra_pwr_domain_suspend,
275 .pwr_domain_on_finish = tegra_pwr_domain_on_finish,
276 .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish,
Varun Wadekard22429d2016-03-18 14:35:28 -0700277 .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi,
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530278 .system_off = tegra_system_off,
279 .system_reset = tegra_system_reset,
280 .validate_power_state = tegra_validate_power_state,
281 .validate_ns_entrypoint = tegra_validate_ns_entrypoint,
282 .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state,
Varun Wadekarb316e242015-05-19 16:48:04 +0530283};
284
285/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530286 * Export the platform specific power ops and initialize Power Controller
Varun Wadekarb316e242015-05-19 16:48:04 +0530287 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530288int plat_setup_psci_ops(uintptr_t sec_entrypoint,
289 const plat_psci_ops_t **psci_ops)
Varun Wadekarb316e242015-05-19 16:48:04 +0530290{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530291 psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } };
292
293 /*
294 * Flush entrypoint variable to PoC since it will be
295 * accessed after a reset with the caches turned off.
296 */
297 tegra_sec_entry_point = sec_entrypoint;
298 flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t));
299
Varun Wadekarb316e242015-05-19 16:48:04 +0530300 /*
301 * Reset hardware settings.
302 */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800303 (void)tegra_soc_pwr_domain_on_finish(&target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530304
305 /*
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700306 * Disable System Suspend if the platform does not
307 * support it
308 */
309 if (!plat_supports_system_suspend()) {
310 tegra_plat_psci_ops.get_sys_suspend_power_state = NULL;
311 }
312
313 /*
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530314 * Initialize PSCI ops struct
Varun Wadekarb316e242015-05-19 16:48:04 +0530315 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530316 *psci_ops = &tegra_plat_psci_ops;
Varun Wadekarb316e242015-05-19 16:48:04 +0530317
318 return 0;
319}
Varun Wadekar24975392016-05-05 14:13:30 -0700320
321/*******************************************************************************
322 * Platform handler to calculate the proper target power level at the
323 * specified affinity level
324 ******************************************************************************/
325plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
326 const plat_local_state_t *states,
327 unsigned int ncpu)
328{
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700329 return tegra_soc_get_target_pwr_state(lvl, states, ncpu);
Varun Wadekar24975392016-05-05 14:13:30 -0700330}