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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7c6df5b2018-01-15 14:43:42 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch.h>
8#include <arm_def.h>
Antonio Nino Diazf09d0032017-04-11 14:04:56 +01009#include <arm_xlat_tables.h>
Roberto Vargas2ca18d92018-02-12 12:36:17 +000010#include <bl1.h>
Dan Handley9df48042015-03-19 18:58:55 +000011#include <bl_common.h>
Dan Handley9df48042015-03-19 18:58:55 +000012#include <plat_arm.h>
Roberto Vargas2ca18d92018-02-12 12:36:17 +000013#include <platform.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010014#include <platform_def.h>
Juan Castillob6132f12015-10-06 14:01:35 +010015#include <sp805.h>
Sandrine Bailleux28ee10f2016-06-15 15:44:27 +010016#include <utils.h>
Sandrine Bailleuxd7c47502015-10-02 09:32:35 +010017#include "../../../bl1/bl1_private.h"
Dan Handley9df48042015-03-19 18:58:55 +000018
Dan Handley9df48042015-03-19 18:58:55 +000019/* Weak definitions may be overridden in specific ARM standard platform */
20#pragma weak bl1_early_platform_setup
21#pragma weak bl1_plat_arch_setup
22#pragma weak bl1_platform_setup
23#pragma weak bl1_plat_sec_mem_layout
Yatharth Kocharede39cb2016-11-14 12:01:04 +000024#pragma weak bl1_plat_prepare_exit
Dan Handley9df48042015-03-19 18:58:55 +000025
26
27/* Data structure which holds the extents of the trusted SRAM for BL1*/
28static meminfo_t bl1_tzram_layout;
29
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020030struct meminfo *bl1_plat_sec_mem_layout(void)
Dan Handley9df48042015-03-19 18:58:55 +000031{
32 return &bl1_tzram_layout;
33}
34
35/*******************************************************************************
36 * BL1 specific platform actions shared between ARM standard platforms.
37 ******************************************************************************/
38void arm_bl1_early_platform_setup(void)
39{
Dan Handley9df48042015-03-19 18:58:55 +000040
Juan Castillob6132f12015-10-06 14:01:35 +010041#if !ARM_DISABLE_TRUSTED_WDOG
42 /* Enable watchdog */
43 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
44#endif
45
Dan Handley9df48042015-03-19 18:58:55 +000046 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010047 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000048
49 /* Allow BL1 to see the whole Trusted RAM */
50 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
51 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
52
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010053#if !LOAD_IMAGE_V2
Dan Handley9df48042015-03-19 18:58:55 +000054 /* Calculate how much RAM BL1 is using and how much remains free */
55 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE;
56 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE;
57 reserve_mem(&bl1_tzram_layout.free_base,
58 &bl1_tzram_layout.free_size,
59 BL1_RAM_BASE,
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010060 BL1_RAM_LIMIT - BL1_RAM_BASE);
61#endif /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +000062}
63
64void bl1_early_platform_setup(void)
65{
66 arm_bl1_early_platform_setup();
67
68 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000069 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +000070 * No need for locks as no other CPU is active.
71 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000072 plat_arm_interconnect_init();
Dan Handley9df48042015-03-19 18:58:55 +000073 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000074 * Enable Interconnect coherency for the primary CPU's cluster.
Dan Handley9df48042015-03-19 18:58:55 +000075 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000076 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +000077}
78
79/******************************************************************************
80 * Perform the very early platform specific architecture setup shared between
81 * ARM standard platforms. This only does basic initialization. Later
82 * architectural setup (bl1_arch_setup()) does not do anything platform
83 * specific.
84 *****************************************************************************/
85void arm_bl1_plat_arch_setup(void)
86{
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010087 arm_setup_page_tables(bl1_tzram_layout.total_base,
Dan Handley9df48042015-03-19 18:58:55 +000088 bl1_tzram_layout.total_size,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010089 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +090090 BL1_CODE_END,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010091 BL1_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +090092 BL1_RO_DATA_END
Dan Handley9df48042015-03-19 18:58:55 +000093#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +090094 , BL_COHERENT_RAM_BASE,
95 BL_COHERENT_RAM_END
Dan Handley9df48042015-03-19 18:58:55 +000096#endif
97 );
Yatharth Kochar88ac53b2016-07-04 11:03:49 +010098#ifdef AARCH32
99 enable_mmu_secure(0);
100#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100101 enable_mmu_el3(0);
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100102#endif /* AARCH32 */
Dan Handley9df48042015-03-19 18:58:55 +0000103}
104
105void bl1_plat_arch_setup(void)
106{
107 arm_bl1_plat_arch_setup();
108}
109
110/*
111 * Perform the platform specific architecture setup shared between
112 * ARM standard platforms.
113 */
114void arm_bl1_platform_setup(void)
115{
116 /* Initialise the IO layer and register platform IO devices */
117 plat_arm_io_setup();
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000118#if LOAD_IMAGE_V2
119 arm_load_tb_fw_config();
120#endif
Soby Mathewd969a7e2018-06-11 16:40:36 +0100121 /*
122 * Allow access to the System counter timer module and program
123 * counter frequency for non secure images during FWU
124 */
125 arm_configure_sys_timer();
126 write_cntfrq_el0(plat_get_syscnt_freq2());
Dan Handley9df48042015-03-19 18:58:55 +0000127}
128
129void bl1_platform_setup(void)
130{
131 arm_bl1_platform_setup();
132}
133
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000134void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
135{
Juan Castillob6132f12015-10-06 14:01:35 +0100136#if !ARM_DISABLE_TRUSTED_WDOG
137 /* Disable watchdog before leaving BL1 */
138 sp805_stop(ARM_SP805_TWDG_BASE);
139#endif
140
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000141#ifdef EL3_PAYLOAD_BASE
142 /*
143 * Program the EL3 payload's entry point address into the CPUs mailbox
144 * in order to release secondary CPUs from their holding pen and make
145 * them jump there.
146 */
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100147 plat_arm_program_trusted_mailbox(ep_info->pc);
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000148 dsbsy();
149 sev();
150#endif
151}
Soby Mathew94273572018-03-07 11:32:04 +0000152
153/*******************************************************************************
154 * The following function checks if Firmware update is needed,
155 * by checking if TOC in FIP image is valid or not.
156 ******************************************************************************/
157unsigned int bl1_plat_get_next_image_id(void)
158{
159 if (!arm_io_is_toc_valid())
160 return NS_BL1U_IMAGE_ID;
161
162 return BL2_IMAGE_ID;
163}