Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 2 | * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 7 | #ifndef __CORTEX_A53_H__ |
| 8 | #define __CORTEX_A53_H__ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 10 | /* Cortex-A53 midr for revision 0 */ |
| 11 | #define CORTEX_A53_MIDR 0x410FD030 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 12 | |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 13 | /* Retention timer tick definitions */ |
| 14 | #define RETENTION_ENTRY_TICKS_2 0x1 |
| 15 | #define RETENTION_ENTRY_TICKS_8 0x2 |
| 16 | #define RETENTION_ENTRY_TICKS_32 0x3 |
| 17 | #define RETENTION_ENTRY_TICKS_64 0x4 |
| 18 | #define RETENTION_ENTRY_TICKS_128 0x5 |
| 19 | #define RETENTION_ENTRY_TICKS_256 0x6 |
| 20 | #define RETENTION_ENTRY_TICKS_512 0x7 |
| 21 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 22 | /******************************************************************************* |
| 23 | * CPU Extended Control register specific definitions. |
| 24 | ******************************************************************************/ |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 25 | #define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ |
| 26 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 27 | #define CPUECTLR_SMP_BIT (1 << 6) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 28 | |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 29 | #define CPUECTLR_CPU_RET_CTRL_SHIFT 0 |
| 30 | #define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) |
| 31 | |
| 32 | #define CPUECTLR_FPU_RET_CTRL_SHIFT 3 |
| 33 | #define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) |
| 34 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 35 | /******************************************************************************* |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 36 | * CPU Memory Error Syndrome register specific definitions. |
| 37 | ******************************************************************************/ |
| 38 | #define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ |
| 39 | |
| 40 | /******************************************************************************* |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 41 | * CPU Auxiliary Control register specific definitions. |
| 42 | ******************************************************************************/ |
| 43 | #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ |
| 44 | |
Haojian Zhuang | 9326b90 | 2017-05-24 08:48:57 +0800 | [diff] [blame^] | 45 | #define CPUACTLR_ENDCCASCI_SHIFT 44 |
| 46 | #define CPUACTLR_ENDCCASCI (1 << CPUACTLR_ENDCCASCI_SHIFT) |
| 47 | #define CPUACTLR_RADIS_SHIFT 27 |
| 48 | #define CPUACTLR_RADIS (3 << CPUACTLR_RADIS_SHIFT) |
| 49 | #define CPUACTLR_L1RADIS_SHIFT 25 |
| 50 | #define CPUACTLR_L1RADIS (3 << CPUACTLR_L1RADIS_SHIFT) |
| 51 | #define CPUACTLR_DTAH_SHIFT 24 |
| 52 | #define CPUACTLR_DTAH (1 << CPUACTLR_DTAH_SHIFT) |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 53 | |
| 54 | /******************************************************************************* |
| 55 | * L2 Auxiliary Control register specific definitions. |
| 56 | ******************************************************************************/ |
| 57 | #define L2ACTLR_EL1 S3_1_C15_C0_0 /* Instruction def. */ |
| 58 | |
| 59 | #define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) |
| 60 | #define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) |
| 61 | |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 62 | /******************************************************************************* |
| 63 | * L2 Extended Control register specific definitions. |
| 64 | ******************************************************************************/ |
| 65 | #define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */ |
| 66 | |
| 67 | #define L2ECTLR_RET_CTRL_SHIFT 0 |
| 68 | #define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) |
| 69 | |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 70 | /******************************************************************************* |
| 71 | * L2 Memory Error Syndrome register specific definitions. |
| 72 | ******************************************************************************/ |
| 73 | #define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ |
| 74 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 75 | #endif /* __CORTEX_A53_H__ */ |