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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathewc704cbc2014-08-14 11:33:56 +01002 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
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8 * list of conditions and the following disclaimer.
9 *
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11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
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14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
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17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29 */
30
Soby Mathew8e2f2872014-08-14 12:49:05 +010031#ifndef __CORTEX_A53_H__
32#define __CORTEX_A53_H__
Achin Gupta4f6ad662013-10-25 09:08:21 +010033
Soby Mathew8e2f2872014-08-14 12:49:05 +010034/* Cortex-A53 midr for revision 0 */
35#define CORTEX_A53_MIDR 0x410FD030
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
Soby Mathew8e2f2872014-08-14 12:49:05 +010037/*******************************************************************************
38 * CPU Extended Control register specific definitions.
39 ******************************************************************************/
40#define CPUECTLR_SMP_BIT (1 << 6)
Achin Gupta4f6ad662013-10-25 09:08:21 +010041
Soby Mathew8e2f2872014-08-14 12:49:05 +010042#endif /* __CORTEX_A53_H__ */