Robert Marko | 9c523ec | 2021-10-11 16:25:49 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2021 Sartura Ltd. |
| 3 | * Copyright (C) 2021 Globalscale technologies, Inc. |
| 4 | * Copyright (C) 2021 Marvell International Ltd. |
| 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | * https://spdx.org/licenses |
| 8 | */ |
| 9 | |
| 10 | #include <arch_helpers.h> |
| 11 | #include <common/debug.h> |
| 12 | |
| 13 | #include <mv_ddr_if.h> |
| 14 | #include <plat_marvell.h> |
| 15 | |
| 16 | /* |
| 17 | * This function may modify the default DRAM parameters |
| 18 | * based on information received from SPD or bootloader |
| 19 | * configuration located on non volatile storage |
| 20 | */ |
| 21 | void plat_marvell_dram_update_topology(void) |
| 22 | { |
| 23 | } |
| 24 | |
| 25 | /* |
| 26 | * This struct provides the DRAM training code with |
| 27 | * the appropriate board DRAM configuration |
| 28 | */ |
| 29 | #if DDR_TOPOLOGY == 0 |
| 30 | static struct mv_ddr_topology_map board_topology_map_2g = { |
| 31 | /* 1CS 4Gb x4 devices of Samsung K4A4G085WF */ |
| 32 | DEBUG_LEVEL_ERROR, |
| 33 | 0x1, /* active interfaces */ |
| 34 | /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ |
| 35 | { { { {0x1, 0x2, 0, 0}, |
| 36 | {0x1, 0x2, 0, 0}, |
| 37 | {0x1, 0x2, 0, 0}, |
| 38 | {0x1, 0x2, 0, 0}, |
| 39 | {0x1, 0x2, 0, 0}, |
| 40 | {0x1, 0x2, 0, 0}, |
| 41 | {0x1, 0x2, 0, 0}, |
| 42 | {0x1, 0x2, 0, 0}, |
| 43 | {0x1, 0x2, 0, 0} }, |
| 44 | SPEED_BIN_DDR_2400R, /* speed_bin */ |
| 45 | MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */ |
| 46 | MV_DDR_DIE_CAP_4GBIT, /* die capacity */ |
| 47 | MV_DDR_FREQ_SAR, /* frequency */ |
| 48 | 0, 0, /* cas_l, cas_wl */ |
| 49 | MV_DDR_TEMP_LOW} }, /* temperature */ |
| 50 | BUS_MASK_32BIT, /* subphys mask */ |
| 51 | MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ |
| 52 | NOT_COMBINED, /* ddr twin-die combined*/ |
| 53 | { {0} }, /* raw spd data */ |
| 54 | {0}, /* timing parameters */ |
| 55 | { /* electrical configuration */ |
| 56 | { /* memory electrical configuration */ |
| 57 | MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ |
| 58 | { |
| 59 | MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ |
| 60 | MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ |
| 61 | }, |
| 62 | { |
| 63 | MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ |
| 64 | MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */ |
| 65 | }, |
| 66 | MV_DDR_DIC_RZQ_DIV7 /* dic */ |
| 67 | }, |
| 68 | { /* phy electrical configuration */ |
| 69 | MV_DDR_OHM_30, /* data_drv_p */ |
| 70 | MV_DDR_OHM_30, /* data_drv_n */ |
| 71 | MV_DDR_OHM_30, /* ctrl_drv_p */ |
| 72 | MV_DDR_OHM_30, /* ctrl_drv_n */ |
| 73 | { |
| 74 | MV_DDR_OHM_60, /* odt_p 1cs */ |
| 75 | MV_DDR_OHM_120 /* odt_p 2cs */ |
| 76 | }, |
| 77 | { |
| 78 | MV_DDR_OHM_60, /* odt_n 1cs */ |
| 79 | MV_DDR_OHM_120 /* odt_n 2cs */ |
| 80 | }, |
| 81 | }, |
| 82 | { /* mac electrical configuration */ |
| 83 | MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ |
| 84 | MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ |
| 85 | MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ |
| 86 | }, |
| 87 | } |
| 88 | }; |
| 89 | #endif |
| 90 | |
| 91 | #if DDR_TOPOLOGY == 1 |
| 92 | static struct mv_ddr_topology_map board_topology_map_4g = { |
| 93 | /* 1CS 8Gb x4 devices of Samsung K4A8G085WC-BCTD */ |
| 94 | DEBUG_LEVEL_ERROR, |
| 95 | 0x1, /* active interfaces */ |
| 96 | /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ |
| 97 | { { { {0x1, 0x2, 0, 0}, |
| 98 | {0x1, 0x2, 0, 0}, |
| 99 | {0x1, 0x2, 0, 0}, |
| 100 | {0x1, 0x2, 0, 0}, |
| 101 | {0x1, 0x2, 0, 0}, |
| 102 | {0x1, 0x2, 0, 0}, |
| 103 | {0x1, 0x2, 0, 0}, |
| 104 | {0x1, 0x2, 0, 0}, |
| 105 | {0x1, 0x2, 0, 0} }, |
| 106 | SPEED_BIN_DDR_2400R, /* speed_bin */ |
| 107 | MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */ |
| 108 | MV_DDR_DIE_CAP_8GBIT, /* die capacity */ |
| 109 | MV_DDR_FREQ_SAR, /* frequency */ |
| 110 | 0, 0, /* cas_l, cas_wl */ |
| 111 | MV_DDR_TEMP_LOW} }, /* temperature */ |
| 112 | BUS_MASK_32BIT, /* subphys mask */ |
| 113 | MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ |
| 114 | NOT_COMBINED, /* ddr twin-die combined*/ |
| 115 | { {0} }, /* raw spd data */ |
| 116 | {0}, /* timing parameters */ |
| 117 | { /* electrical configuration */ |
| 118 | { /* memory electrical configuration */ |
| 119 | MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ |
| 120 | { |
| 121 | MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ |
| 122 | MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ |
| 123 | }, |
| 124 | { |
| 125 | MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ |
| 126 | MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */ |
| 127 | }, |
| 128 | MV_DDR_DIC_RZQ_DIV7 /* dic */ |
| 129 | }, |
| 130 | { /* phy electrical configuration */ |
| 131 | MV_DDR_OHM_30, /* data_drv_p */ |
| 132 | MV_DDR_OHM_30, /* data_drv_n */ |
| 133 | MV_DDR_OHM_30, /* ctrl_drv_p */ |
| 134 | MV_DDR_OHM_30, /* ctrl_drv_n */ |
| 135 | { |
| 136 | MV_DDR_OHM_60, /* odt_p 1cs */ |
| 137 | MV_DDR_OHM_120 /* odt_p 2cs */ |
| 138 | }, |
| 139 | { |
| 140 | MV_DDR_OHM_60, /* odt_n 1cs */ |
| 141 | MV_DDR_OHM_120 /* odt_n 2cs */ |
| 142 | }, |
| 143 | }, |
| 144 | { /* mac electrical configuration */ |
| 145 | MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ |
| 146 | MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ |
| 147 | MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ |
| 148 | }, |
| 149 | } |
| 150 | }; |
| 151 | #endif |
| 152 | |
| 153 | #if DDR_TOPOLOGY == 2 |
| 154 | static struct mv_ddr_topology_map board_topology_map_8g = { |
| 155 | /* 2CS 8Gb x8 devices of Micron MT40A1G8WE-083E IT */ |
| 156 | DEBUG_LEVEL_ERROR, |
| 157 | 0x1, /* active interfaces */ |
| 158 | /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ |
| 159 | { { { {0x3, 0x2, 0, 0}, |
| 160 | {0x3, 0x2, 0, 0}, |
| 161 | {0x3, 0x2, 0, 0}, |
| 162 | {0x3, 0x2, 0, 0}, |
| 163 | {0x3, 0x2, 0, 0}, |
| 164 | {0x3, 0x2, 0, 0}, |
| 165 | {0x3, 0x2, 0, 0}, |
| 166 | {0x3, 0x2, 0, 0}, |
| 167 | {0x3, 0x2, 0, 0} }, |
| 168 | SPEED_BIN_DDR_2400R, /* speed_bin */ |
| 169 | MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */ |
| 170 | MV_DDR_DIE_CAP_8GBIT, /* die capacity */ |
| 171 | MV_DDR_FREQ_SAR, /* frequency */ |
| 172 | 0, 0, /* cas_l, cas_wl */ |
| 173 | MV_DDR_TEMP_LOW} }, /* temperature */ |
| 174 | BUS_MASK_32BIT, /* subphys mask */ |
| 175 | MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ |
| 176 | NOT_COMBINED, /* ddr twin-die combined*/ |
| 177 | { {0} }, /* raw spd data */ |
| 178 | {0}, /* timing parameters */ |
| 179 | { /* electrical configuration */ |
| 180 | { /* memory electrical configuration */ |
| 181 | MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ |
| 182 | { |
| 183 | MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ |
| 184 | MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ |
| 185 | }, |
| 186 | { |
| 187 | MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ |
| 188 | MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */ |
| 189 | }, |
| 190 | MV_DDR_DIC_RZQ_DIV7 /* dic */ |
| 191 | }, |
| 192 | { /* phy electrical configuration */ |
| 193 | MV_DDR_OHM_30, /* data_drv_p */ |
| 194 | MV_DDR_OHM_30, /* data_drv_n */ |
| 195 | MV_DDR_OHM_30, /* ctrl_drv_p */ |
| 196 | MV_DDR_OHM_30, /* ctrl_drv_n */ |
| 197 | { |
| 198 | MV_DDR_OHM_60, /* odt_p 1cs */ |
| 199 | MV_DDR_OHM_120 /* odt_p 2cs */ |
| 200 | }, |
| 201 | { |
| 202 | MV_DDR_OHM_60, /* odt_n 1cs */ |
| 203 | MV_DDR_OHM_120 /* odt_n 2cs */ |
| 204 | }, |
| 205 | }, |
| 206 | { /* mac electrical configuration */ |
| 207 | MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ |
| 208 | MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ |
| 209 | MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ |
| 210 | }, |
| 211 | } |
| 212 | }; |
| 213 | #endif |
| 214 | |
| 215 | struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) |
| 216 | { |
| 217 | /* a70x0_mochabin board supports 3 DDR4 models (2G/1CS, 4G/1CS, 8G/2CS) */ |
| 218 | #if DDR_TOPOLOGY == 0 |
| 219 | return &board_topology_map_2g; |
| 220 | #elif DDR_TOPOLOGY == 1 |
| 221 | return &board_topology_map_4g; |
| 222 | #elif DDR_TOPOLOGY == 2 |
| 223 | return &board_topology_map_8g; |
| 224 | #else |
| 225 | #error "Unknown DDR topology" |
| 226 | #endif |
| 227 | } |