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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Masahiro Yamada43d20b32018-02-01 16:46:18 +09002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01008#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +01009#include <assert.h>
Juan Castilloa08a5e72015-05-19 11:54:12 +010010#include <auth_mod.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010011#include <bl1.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010012#include <bl_common.h>
Antonio Nino Diaze3962d02017-02-16 16:17:19 +000013#include <console.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010014#include <debug.h>
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000015#include <errata_report.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010016#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010017#include <platform_def.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010018#include <smcc_helpers.h>
Soby Mathewc53ac5e2016-07-20 14:38:36 +010019#include <utils.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010020#include <uuid.h>
Isla Mitchell99305012017-07-11 14:54:08 +010021#include "bl1_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010022
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010023/* BL1 Service UUID */
24DEFINE_SVC_UUID(bl1_svc_uid,
25 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75,
26 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
27
Yatharth Kochara65be2f2015-10-09 18:06:13 +010028static void bl1_load_bl2(void);
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010029
Sandrine Bailleux467d0572014-06-24 14:02:34 +010030/*******************************************************************************
Soby Mathew6e16a332018-01-10 12:51:34 +000031 * Helper utility to calculate the BL2 memory layout taking into consideration
32 * the BL1 RW data assuming that it is at the top of the memory layout.
Sandrine Bailleux467d0572014-06-24 14:02:34 +010033 ******************************************************************************/
Soby Mathew6e16a332018-01-10 12:51:34 +000034void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
35 meminfo_t *bl2_mem_layout)
Sandrine Bailleux467d0572014-06-24 14:02:34 +010036{
Sandrine Bailleux467d0572014-06-24 14:02:34 +010037 assert(bl1_mem_layout != NULL);
38 assert(bl2_mem_layout != NULL);
39
Yatharth Kochar51f76f62016-09-12 16:10:33 +010040#if LOAD_IMAGE_V2
41 /*
42 * Remove BL1 RW data from the scope of memory visible to BL2.
43 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
44 */
45 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
46 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
47 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
48#else
Sandrine Bailleux467d0572014-06-24 14:02:34 +010049 /* Check that BL1's memory is lying outside of the free memory */
50 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
Yatharth Kochara65be2f2015-10-09 18:06:13 +010051 (BL1_RAM_BASE >= bl1_mem_layout->free_base +
52 bl1_mem_layout->free_size));
Sandrine Bailleux467d0572014-06-24 14:02:34 +010053
54 /* Remove BL1 RW data from the scope of memory visible to BL2 */
55 *bl2_mem_layout = *bl1_mem_layout;
56 reserve_mem(&bl2_mem_layout->total_base,
57 &bl2_mem_layout->total_size,
58 BL1_RAM_BASE,
Yatharth Kochar51f76f62016-09-12 16:10:33 +010059 BL1_RAM_LIMIT - BL1_RAM_BASE);
60#endif /* LOAD_IMAGE_V2 */
Sandrine Bailleux467d0572014-06-24 14:02:34 +010061
62 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
63}
Soby Mathew6e16a332018-01-10 12:51:34 +000064
65#if !ERROR_DEPRECATED
66/*******************************************************************************
67 * Compatibility default implementation for deprecated API. This has a weak
68 * definition. Platform specific code can override it if it wishes to.
69 ******************************************************************************/
70#pragma weak bl1_init_bl2_mem_layout
71
72/*******************************************************************************
73 * Function that takes a memory layout into which BL2 has been loaded and
74 * populates a new memory layout for BL2 that ensures that BL1's data sections
75 * resident in secure RAM are not visible to BL2.
76 ******************************************************************************/
77void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
78 meminfo_t *bl2_mem_layout)
79{
80 bl1_calc_bl2_mem_layout(bl1_mem_layout, bl2_mem_layout);
81}
82#endif
Sandrine Bailleux467d0572014-06-24 14:02:34 +010083
84/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010085 * Function to perform late architectural and platform specific initialization.
Yatharth Kochara65be2f2015-10-09 18:06:13 +010086 * It also queries the platform to load and run next BL image. Only called
87 * by the primary cpu after a cold boot.
88 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +010089void bl1_main(void)
90{
Yatharth Kochara65be2f2015-10-09 18:06:13 +010091 unsigned int image_id;
92
Dan Handley91b624e2014-07-29 17:14:00 +010093 /* Announce our arrival */
94 NOTICE(FIRMWARE_WELCOME_STR);
95 NOTICE("BL1: %s\n", version_string);
96 NOTICE("BL1: %s\n", build_message);
97
Yatharth Kochar5d361212016-06-28 17:07:09 +010098 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE,
99 (void *)BL1_RAM_LIMIT);
Dan Handley91b624e2014-07-29 17:14:00 +0100100
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +0000101 print_errata_status();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100102
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +0000103#if ENABLE_ASSERTIONS
Yatharth Kochar5d361212016-06-28 17:07:09 +0100104 u_register_t val;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105 /*
106 * Ensure that MMU/Caches and coherency are turned on
107 */
Yatharth Kochar5d361212016-06-28 17:07:09 +0100108#ifdef AARCH32
109 val = read_sctlr();
110#else
Dan Handley0cdebbd2015-03-30 17:15:16 +0100111 val = read_sctlr_el3();
Yatharth Kochar5d361212016-06-28 17:07:09 +0100112#endif
Andrew Thoelke5e287b52015-06-11 14:12:14 +0100113 assert(val & SCTLR_M_BIT);
114 assert(val & SCTLR_C_BIT);
115 assert(val & SCTLR_I_BIT);
Dan Handley0cdebbd2015-03-30 17:15:16 +0100116 /*
117 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
118 * provided platform value
119 */
120 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
121 /*
122 * If CWG is zero, then no CWG information is available but we can
123 * at least check the platform value is less than the architectural
124 * maximum.
125 */
126 if (val != 0)
127 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
128 else
129 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +0000130#endif /* ENABLE_ASSERTIONS */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100131
132 /* Perform remaining generic architectural setup from EL3 */
133 bl1_arch_setup();
134
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100135#if TRUSTED_BOARD_BOOT
136 /* Initialize authentication module */
137 auth_mod_init();
138#endif /* TRUSTED_BOARD_BOOT */
139
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140 /* Perform platform setup in BL1. */
141 bl1_platform_setup();
142
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100143 /* Get the image id of next image to load and run. */
144 image_id = bl1_plat_get_next_image_id();
145
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100146 /*
147 * We currently interpret any image id other than
148 * BL2_IMAGE_ID as the start of firmware update.
149 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100150 if (image_id == BL2_IMAGE_ID)
151 bl1_load_bl2();
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100152 else
153 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100154
155 bl1_prepare_next_image(image_id);
Antonio Nino Diaze3962d02017-02-16 16:17:19 +0000156
157 console_flush();
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100158}
159
160/*******************************************************************************
161 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
162 * Called by the primary cpu after a cold boot.
163 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
164 * loader etc.
165 ******************************************************************************/
Roberto Vargasbcfaeff2018-02-12 12:36:17 +0000166static void bl1_load_bl2(void)
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100167{
168 image_desc_t *image_desc;
169 image_info_t *image_info;
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100170 int err;
171
172 /* Get the image descriptor */
173 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
174 assert(image_desc);
175
176 /* Get the image info */
177 image_info = &image_desc->image_info;
Juan Castillo3a66aca2015-04-13 17:36:19 +0100178 INFO("BL1: Loading BL2\n");
179
Soby Mathew2f38ce32018-02-08 17:45:12 +0000180 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
Masahiro Yamada43d20b32018-02-01 16:46:18 +0900181 if (err) {
182 ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
183 plat_error_handler(err);
184 }
185
Soby Mathew2f38ce32018-02-08 17:45:12 +0000186#if LOAD_IMAGE_V2
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100187 err = load_auth_image(BL2_IMAGE_ID, image_info);
188#else
Soby Mathew6e16a332018-01-10 12:51:34 +0000189 entry_point_info_t *ep_info;
190 meminfo_t *bl1_tzram_layout;
191
192 /* Get the entry point info */
193 ep_info = &image_desc->ep_info;
194
195 /* Find out how much free trusted ram remains after BL1 load */
196 bl1_tzram_layout = bl1_plat_sec_mem_layout();
197
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100198 /* Load the BL2 image */
Juan Castilloa08a5e72015-05-19 11:54:12 +0100199 err = load_auth_image(bl1_tzram_layout,
Juan Castillo3a66aca2015-04-13 17:36:19 +0100200 BL2_IMAGE_ID,
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100201 image_info->image_base,
202 image_info,
203 ep_info);
Juan Castilloa08a5e72015-05-19 11:54:12 +0100204
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100205#endif /* LOAD_IMAGE_V2 */
206
Vikram Kanigirida567432014-04-15 18:08:08 +0100207 if (err) {
Dan Handley91b624e2014-07-29 17:14:00 +0100208 ERROR("Failed to load BL2 firmware.\n");
Juan Castillo26ae5832015-09-25 15:41:14 +0100209 plat_error_handler(err);
Vikram Kanigirida567432014-04-15 18:08:08 +0100210 }
Juan Castillod227d8b2015-01-07 13:49:59 +0000211
Masahiro Yamada43d20b32018-02-01 16:46:18 +0900212 /* Allow platform to handle image information. */
Soby Mathew2f38ce32018-02-08 17:45:12 +0000213 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
Masahiro Yamada43d20b32018-02-01 16:46:18 +0900214 if (err) {
215 ERROR("Failure in post image load handling of BL2 (%d)\n", err);
216 plat_error_handler(err);
217 }
218
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100219 NOTICE("BL1: Booting BL2\n");
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220}
221
222/*******************************************************************************
Yatharth Kochar5d361212016-06-28 17:07:09 +0100223 * Function called just before handing over to the next BL to inform the user
224 * about the boot progress. In debug mode, also print details about the BL
225 * image's execution context.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100226 ******************************************************************************/
Yatharth Kochar5d361212016-06-28 17:07:09 +0100227void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100228{
Yatharth Kochar5d361212016-06-28 17:07:09 +0100229#ifdef AARCH32
230 NOTICE("BL1: Booting BL32\n");
231#else
Juan Castillo7d199412015-12-14 09:35:25 +0000232 NOTICE("BL1: Booting BL31\n");
Yatharth Kochar5d361212016-06-28 17:07:09 +0100233#endif /* AARCH32 */
234 print_entry_point_info(bl_ep_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100235}
Sandrine Bailleuxb7e97c42015-11-10 10:01:19 +0000236
237#if SPIN_ON_BL1_EXIT
238void print_debug_loop_message(void)
239{
240 NOTICE("BL1: Debug loop, spinning forever\n");
241 NOTICE("BL1: Please connect the debugger to continue\n");
242}
243#endif
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100244
245/*******************************************************************************
246 * Top level handler for servicing BL1 SMCs.
247 ******************************************************************************/
248register_t bl1_smc_handler(unsigned int smc_fid,
249 register_t x1,
250 register_t x2,
251 register_t x3,
252 register_t x4,
253 void *cookie,
254 void *handle,
255 unsigned int flags)
256{
257
258#if TRUSTED_BOARD_BOOT
259 /*
260 * Dispatch FWU calls to FWU SMC handler and return its return
261 * value
262 */
263 if (is_fwu_fid(smc_fid)) {
264 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
265 handle, flags);
266 }
267#endif
268
269 switch (smc_fid) {
270 case BL1_SMC_CALL_COUNT:
271 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
272
273 case BL1_SMC_UID:
274 SMC_UUID_RET(handle, bl1_svc_uid);
275
276 case BL1_SMC_VERSION:
277 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
278
279 default:
280 break;
281 }
282
283 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
284 SMC_RET1(handle, SMC_UNK);
285}
dp-armcdd03cb2017-02-15 11:07:55 +0000286
287/*******************************************************************************
288 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
289 * compliance when invoking bl1_smc_handler.
290 ******************************************************************************/
291register_t bl1_smc_wrapper(uint32_t smc_fid,
292 void *cookie,
293 void *handle,
294 unsigned int flags)
295{
296 register_t x1, x2, x3, x4;
297
298 assert(handle);
299
300 get_smc_params_from_ctx(handle, x1, x2, x3, x4);
301 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
302}