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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000031#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000032#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <bl_common.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35 .globl bl31_entrypoint
36
37
Achin Gupta4f6ad662013-10-25 09:08:21 +010038 /* -----------------------------------------------------
39 * bl31_entrypoint() is the cold boot entrypoint,
40 * executed only by the primary cpu.
41 * -----------------------------------------------------
42 */
43
Andrew Thoelke38bde412014-03-18 13:46:55 +000044func bl31_entrypoint
Vikram Kanigirida567432014-04-15 18:08:08 +010045 /* ---------------------------------------------------------------
46 * Preceding bootloader has populated x0 with a pointer to a
47 * 'bl31_params' structure & x1 with a pointer to platform
48 * specific structure
49 * ---------------------------------------------------------------
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000050 */
Vikram Kanigiri96377452014-04-24 11:02:16 +010051#if !RESET_TO_BL31
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010052 mov x20, x0
53 mov x21, x1
Vikram Kanigiri96377452014-04-24 11:02:16 +010054#else
Achin Gupta9f098352014-07-18 18:38:28 +010055 /* ---------------------------------------------
56 * Set the CPU endianness before doing anything
57 * that might involve memory reads or writes.
58 * ---------------------------------------------
59 */
60 mrs x0, sctlr_el3
61 bic x0, x0, #SCTLR_EE_BIT
62 msr sctlr_el3, x0
63 isb
Vikram Kanigiri96377452014-04-24 11:02:16 +010064
65 /* -----------------------------------------------------
66 * Perform any processor specific actions upon reset
67 * e.g. cache, tlb invalidations etc. Override the
68 * Boot ROM(BL0) programming sequence
69 * -----------------------------------------------------
70 */
Soby Mathewc704cbc2014-08-14 11:33:56 +010071 bl reset_handler
Vikram Kanigiri96377452014-04-24 11:02:16 +010072#endif
Vikram Kanigiri96377452014-04-24 11:02:16 +010073 /* ---------------------------------------------
Achin Gupta9f098352014-07-18 18:38:28 +010074 * Enable the instruction cache, stack pointer
75 * and data access alignment checks
Vikram Kanigiri96377452014-04-24 11:02:16 +010076 * ---------------------------------------------
77 */
Achin Gupta9f098352014-07-18 18:38:28 +010078 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
79 mrs x0, sctlr_el3
80 orr x0, x0, x1
81 msr sctlr_el3, x0
Vikram Kanigiri96377452014-04-24 11:02:16 +010082 isb
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000083
84 /* ---------------------------------------------
Soby Mathewc1adbbc2014-06-25 10:07:40 +010085 * Initialise cpu_data early to enable crash
86 * reporting to have access to crash stack.
87 * Since crash reporting depends on cpu_data to
88 * report the unhandled exception, not
89 * doing so can lead to recursive exceptions due
90 * to a NULL TPIDR_EL3
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000091 * ---------------------------------------------
92 */
Soby Mathewc1adbbc2014-06-25 10:07:40 +010093 bl init_cpu_data_ptr
94
95 /* ---------------------------------------------
96 * Set the exception vector.
97 * ---------------------------------------------
98 */
Andrew Thoelke4d2d5532014-06-02 12:38:12 +010099 adr x1, runtime_exceptions
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000100 msr vbar_el3, x1
Achin Guptaed1744e2014-08-04 23:13:10 +0100101 isb
102
103 /* ---------------------------------------------
104 * Enable the SError interrupt now that the
105 * exception vectors have been setup.
106 * ---------------------------------------------
107 */
108 msr daifclr, #DAIF_ABT_BIT
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000109
Harry Liebel4f603682014-01-14 18:11:48 +0000110 /* ---------------------------------------------------------------------
111 * The initial state of the Architectural feature trap register
112 * (CPTR_EL3) is unknown and it must be set to a known state. All
113 * feature traps are disabled. Some bits in this register are marked as
114 * Reserved and should not be modified.
115 *
116 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
117 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
118 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
119 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
120 * access to trace functionality is not supported, this bit is RES0.
121 * CPTR_EL3.TFP: This causes instructions that access the registers
122 * associated with Floating Point and Advanced SIMD execution to trap
123 * to EL3 when executed from any exception level, unless trapped to EL1
124 * or EL2.
125 * ---------------------------------------------------------------------
126 */
127 mrs x1, cptr_el3
128 bic w1, w1, #TCPAC_BIT
129 bic w1, w1, #TTA_BIT
130 bic w1, w1, #TFP_BIT
131 msr cptr_el3, x1
132
Vikram Kanigiri96377452014-04-24 11:02:16 +0100133#if RESET_TO_BL31
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100134 /* -------------------------------------------------------
135 * Will not return from this macro if it is a warm boot.
136 * -------------------------------------------------------
137 */
Vikram Kanigiri96377452014-04-24 11:02:16 +0100138 wait_for_entrypoint
139 bl platform_mem_init
Vikram Kanigiri96377452014-04-24 11:02:16 +0100140#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100141
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000142 /* ---------------------------------------------
143 * Zero out NOBITS sections. There are 2 of them:
144 * - the .bss section;
145 * - the coherent memory section.
146 * ---------------------------------------------
147 */
148 ldr x0, =__BSS_START__
149 ldr x1, =__BSS_SIZE__
150 bl zeromem16
151
152 ldr x0, =__COHERENT_RAM_START__
153 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
154 bl zeromem16
155
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000156 /* ---------------------------------------------
Soby Mathew8e2f2872014-08-14 12:49:05 +0100157 * Initialize the cpu_ops pointer.
158 * ---------------------------------------------
159 */
160 bl init_cpu_ops
161
162 /* ---------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000163 * Use SP_EL0 for the C runtime stack.
164 * ---------------------------------------------
165 */
166 msr spsel, #0
167
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168 /* --------------------------------------------
Achin Guptaf4a97092014-06-25 19:26:22 +0100169 * Allocate a stack whose memory will be marked
170 * as Normal-IS-WBWA when the MMU is enabled.
171 * There is no risk of reading stale stack
172 * memory after enabling the MMU as only the
173 * primary cpu is running at the moment.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174 * --------------------------------------------
175 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100176 mrs x0, mpidr_el1
Achin Guptaf4a97092014-06-25 19:26:22 +0100177 bl platform_set_stack
Achin Gupta4f6ad662013-10-25 09:08:21 +0100178
179 /* ---------------------------------------------
180 * Perform platform specific early arch. setup
181 * ---------------------------------------------
182 */
Vikram Kanigiri96377452014-04-24 11:02:16 +0100183#if RESET_TO_BL31
184 mov x0, 0
185 mov x1, 0
186#else
Achin Gupta4f6ad662013-10-25 09:08:21 +0100187 mov x0, x20
188 mov x1, x21
Vikram Kanigiri96377452014-04-24 11:02:16 +0100189#endif
190
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191 bl bl31_early_platform_setup
192 bl bl31_plat_arch_setup
193
194 /* ---------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000195 * Jump to main function.
Achin Guptab739f222014-01-18 16:50:09 +0000196 * ---------------------------------------------
197 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000198 bl bl31_main
Achin Guptab739f222014-01-18 16:50:09 +0000199
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000200 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100201
202_panic:
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000203 wfi
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204 b _panic