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Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02001/*
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02009
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/interrupt_props.h>
12#include <common/tbbr/tbbr_img_def.h>
13#include <drivers/arm/gic_common.h>
14#include <lib/utils_def.h>
15#include <plat/common/common_def.h>
16
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020017#include "hi3798cv200.h"
18#include "poplar_layout.h" /* BL memory region sizes, etc */
19
Victor Chong175dd8a2018-02-01 00:35:22 +090020/* Special value used to verify platform parameters from BL2 to BL3-1 */
21#define POPLAR_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
22
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020023#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
24#define PLATFORM_LINKER_ARCH aarch64
25
Antonio Nino Diaz6766bb12018-10-26 11:12:31 +010026#define POPLAR_CRASH_UART_BASE PL011_UART0_BASE
27#define POPLAR_CRASH_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ
28#define POPLAR_CONSOLE_BAUDRATE PL011_BAUDRATE
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020029
30/* Generic platform constants */
31#define PLATFORM_STACK_SIZE (0x800)
32
33#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
34#define BOOT_EMMC_NAME "l-loader.bin"
35
36#define PLATFORM_CACHE_LINE_SIZE (64)
37#define PLATFORM_CLUSTER_COUNT (1)
38#define PLATFORM_CORE_COUNT (4)
39#define PLATFORM_MAX_CPUS_PER_CLUSTER (4)
40
41/* IO framework user */
42#define MAX_IO_DEVICES (4)
43#define MAX_IO_HANDLES (4)
Yann Gautier37966212018-12-03 13:38:06 +010044#define MAX_IO_BLOCK_DEVICES U(2)
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020045
Victor Chong50d695d2018-01-29 18:11:02 +090046/* Memory size options */
47#define POPLAR_DRAM_SIZE_1G 0
48#define POPLAR_DRAM_SIZE_2G 1
49
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020050/* Memory map related constants */
51#define DDR_BASE (0x00000000)
Victor Chong50d695d2018-01-29 18:11:02 +090052
53#if (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_2G)
54#define DDR_SIZE (0x80000000)
55#elif (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_1G)
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020056#define DDR_SIZE (0x40000000)
Victor Chong50d695d2018-01-29 18:11:02 +090057#else
58#error "Currently unsupported POPLAR_DRAM_SIZE_ID value"
59#endif
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020060
61#define DEVICE_BASE (0xF0000000)
62#define DEVICE_SIZE (0x0F000000)
63
64#define TEE_SEC_MEM_BASE (0x70000000)
65#define TEE_SEC_MEM_SIZE (0x10000000)
66
Victor Chong662556a2017-10-28 01:59:41 +090067/* Memory location options for TSP */
68#define POPLAR_SRAM_ID 0
69#define POPLAR_DRAM_ID 1
70
71/*
Victor Chong539408d2018-01-03 01:53:08 +090072 * DDR for OP-TEE (26MB from 0x02400000 -0x04000000) is divided in several
Victor Chong662556a2017-10-28 01:59:41 +090073 * regions:
74 * - Secure DDR (default is the top 16MB) used by OP-TEE
75 * - Non-secure DDR (4MB) reserved for OP-TEE's future use
76 * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
77 * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
Victor Chong662556a2017-10-28 01:59:41 +090078 */
79#define DDR_SEC_SIZE 0x01000000
80#define DDR_SEC_BASE 0x03000000
81
Victor Chong662556a2017-10-28 01:59:41 +090082/*
83 * BL3-2 specific defines.
84 */
85
86/*
87 * The TSP currently executes from TZC secured area of DRAM.
88 */
89#define BL32_DRAM_BASE 0x03000000
90#define BL32_DRAM_LIMIT 0x04000000
91
Victor Chongaa033472018-02-01 00:35:39 +090092#ifdef SPD_opteed
93/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
94#define POPLAR_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
95#define POPLAR_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - POPLAR_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x03C0_0000 */
96#endif
Victor Chongaa033472018-02-01 00:35:39 +090097
Victor Chong662556a2017-10-28 01:59:41 +090098#if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID)
99#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
100#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
101#define BL32_BASE BL32_DRAM_BASE
102#define BL32_LIMIT BL32_DRAM_LIMIT
103#elif (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_SRAM_ID)
104#error "SRAM storage of TSP payload is currently unsupported"
105#else
106#error "Currently unsupported POPLAR_TSP_LOCATION_ID value"
107#endif
108
109/* BL32 is mandatory in AArch32 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700110#ifdef __aarch64__
Victor Chong662556a2017-10-28 01:59:41 +0900111#ifdef SPD_none
112#undef BL32_BASE
113#endif /* SPD_none */
114#endif
115
Victor Chong539408d2018-01-03 01:53:08 +0900116#define POPLAR_EMMC_DATA_BASE U(0x02200000)
117#define POPLAR_EMMC_DATA_SIZE EMMC_DESC_SIZE
118#define POPLAR_EMMC_DESC_BASE (POPLAR_EMMC_DATA_BASE + POPLAR_EMMC_DATA_SIZE)
119#define POPLAR_EMMC_DESC_SIZE EMMC_DESC_SIZE
120
Victor Chong6df271c2017-10-27 00:09:14 +0900121#define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200122
123/* Page table and MMU setup constants */
Antonio Nino Diaze93cde12018-09-24 17:15:15 +0100124#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
125#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200126#define MAX_XLAT_TABLES (4)
127#define MAX_MMAP_REGIONS (16)
128
129#define CACHE_WRITEBACK_SHIFT (6)
130#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
131
132/* Power states */
133#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1)
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100134#define PLAT_MAX_OFF_STATE U(2)
135#define PLAT_MAX_RET_STATE U(1)
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200136
137/* Interrupt controller */
Antonio Nino Diaz6766bb12018-10-26 11:12:31 +0100138#define POPLAR_GICD_BASE GICD_BASE
139#define POPLAR_GICC_BASE GICC_BASE
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200140
Antonio Nino Diaz6766bb12018-10-26 11:12:31 +0100141#define POPLAR_G1S_IRQ_PROPS(grp) \
Jeenu Viswambharan0345fc32017-09-29 11:14:02 +0100142 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
143 GIC_INTR_CFG_LEVEL), \
144 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
145 GIC_INTR_CFG_LEVEL), \
146 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
147 GIC_INTR_CFG_LEVEL), \
148 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
149 GIC_INTR_CFG_LEVEL), \
150 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
151 GIC_INTR_CFG_LEVEL), \
152 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
153 GIC_INTR_CFG_LEVEL), \
154 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
155 GIC_INTR_CFG_LEVEL), \
156 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
157 GIC_INTR_CFG_LEVEL), \
158 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER0, GIC_HIGHEST_SEC_PRIORITY, grp, \
159 GIC_INTR_CFG_LEVEL), \
160 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER1, GIC_HIGHEST_SEC_PRIORITY, grp, \
161 GIC_INTR_CFG_LEVEL), \
162 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER2, GIC_HIGHEST_SEC_PRIORITY, grp, \
163 GIC_INTR_CFG_LEVEL), \
164 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER3, GIC_HIGHEST_SEC_PRIORITY, grp, \
165 GIC_INTR_CFG_LEVEL), \
166 INTR_PROP_DESC(HISI_IRQ_SEC_AXI, GIC_HIGHEST_SEC_PRIORITY, grp, \
167 GIC_INTR_CFG_LEVEL)
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200168
Antonio Nino Diaz6766bb12018-10-26 11:12:31 +0100169#define POPLAR_G0_IRQ_PROPS(grp)
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200170
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100171#endif /* PLATFORM_DEF_H */