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Achin Gupta1fa7eb62015-11-03 14:18:34 +00001/*
Roberto Vargas2ca18d92018-02-12 12:36:17 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta1fa7eb62015-11-03 14:18:34 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta1fa7eb62015-11-03 14:18:34 +00005 */
6
7#include <arm_def.h>
8#include <gicv3.h>
Jeenu Viswambharan723dce02017-09-22 08:59:59 +01009#include <interrupt_props.h>
Achin Gupta1fa7eb62015-11-03 14:18:34 +000010#include <plat_arm.h>
11#include <platform.h>
12#include <platform_def.h>
Soby Mathew12cdcd22018-10-12 16:26:20 +010013#include <utils.h>
Achin Gupta1fa7eb62015-11-03 14:18:34 +000014
15/******************************************************************************
16 * The following functions are defined as weak to allow a platform to override
17 * the way the GICv3 driver is initialised and used.
18 *****************************************************************************/
19#pragma weak plat_arm_gic_driver_init
20#pragma weak plat_arm_gic_init
21#pragma weak plat_arm_gic_cpuif_enable
22#pragma weak plat_arm_gic_cpuif_disable
23#pragma weak plat_arm_gic_pcpu_init
Jeenu Viswambharan78132c92016-12-09 11:12:34 +000024#pragma weak plat_arm_gic_redistif_on
25#pragma weak plat_arm_gic_redistif_off
Achin Gupta1fa7eb62015-11-03 14:18:34 +000026
27/* The GICv3 driver only needs to be initialized in EL3 */
Soby Mathewcf022c52016-01-13 17:06:00 +000028static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
Achin Gupta1fa7eb62015-11-03 14:18:34 +000029
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010030static const interrupt_prop_t arm_interrupt_props[] = {
31 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
32 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
Achin Gupta1fa7eb62015-11-03 14:18:34 +000033};
34
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000035/*
Soby Mathew9ca28062017-10-11 16:08:58 +010036 * We save and restore the GICv3 context on system suspend. Allocate the
Soby Mathew12cdcd22018-10-12 16:26:20 +010037 * data in the designated EL3 Secure carve-out memory. The `volatile`
38 * is used to prevent the compiler from removing the gicv3 contexts even
39 * though the DEFINE_LOAD_SYM_ADDR creates a dummy reference to it.
Soby Mathew9ca28062017-10-11 16:08:58 +010040 */
Soby Mathew12cdcd22018-10-12 16:26:20 +010041static volatile gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram");
42static volatile gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram");
43
44/* Define accessor function to get reference to the GICv3 context */
45DEFINE_LOAD_SYM_ADDR(rdist_ctx)
46DEFINE_LOAD_SYM_ADDR(dist_ctx)
Soby Mathew9ca28062017-10-11 16:08:58 +010047
48/*
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000049 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
50 * to core position.
51 *
52 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
53 * values read from GICR_TYPER don't have an MT field. To reuse the same
54 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
55 * that read from GICR_TYPER.
56 *
57 * Assumptions:
58 *
59 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
60 * - No CPUs implemented in the system use affinity level 3.
61 */
62static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
63{
64 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
65 return plat_arm_calc_core_pos(mpidr);
66}
67
Roberto Vargas2ca18d92018-02-12 12:36:17 +000068static const gicv3_driver_data_t arm_gic_data __unused = {
Achin Gupta1fa7eb62015-11-03 14:18:34 +000069 .gicd_base = PLAT_ARM_GICD_BASE,
70 .gicr_base = PLAT_ARM_GICR_BASE,
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010071 .interrupt_props = arm_interrupt_props,
72 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props),
Achin Gupta1fa7eb62015-11-03 14:18:34 +000073 .rdistif_num = PLATFORM_CORE_COUNT,
74 .rdistif_base_addrs = rdistif_base_addrs,
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000075 .mpidr_to_core_pos = arm_gicv3_mpidr_hash
Achin Gupta1fa7eb62015-11-03 14:18:34 +000076};
77
Daniel Boulby844b4872018-09-18 13:36:39 +010078void __init plat_arm_gic_driver_init(void)
Achin Gupta1fa7eb62015-11-03 14:18:34 +000079{
80 /*
81 * The GICv3 driver is initialized in EL3 and does not need
82 * to be initialized again in SEL1. This is because the S-EL1
83 * can use GIC system registers to manage interrupts and does
84 * not need GIC interface base addresses to be configured.
85 */
Masahiro Yamadaa2698372016-12-26 00:22:47 +090086#if (defined(AARCH32) && defined(IMAGE_BL32)) || \
87 (defined(IMAGE_BL31) && !defined(AARCH32))
Achin Gupta1fa7eb62015-11-03 14:18:34 +000088 gicv3_driver_init(&arm_gic_data);
89#endif
90}
91
92/******************************************************************************
93 * ARM common helper to initialize the GIC. Only invoked by BL31
94 *****************************************************************************/
Daniel Boulby844b4872018-09-18 13:36:39 +010095void __init plat_arm_gic_init(void)
Achin Gupta1fa7eb62015-11-03 14:18:34 +000096{
97 gicv3_distif_init();
98 gicv3_rdistif_init(plat_my_core_pos());
99 gicv3_cpuif_enable(plat_my_core_pos());
100}
101
102/******************************************************************************
103 * ARM common helper to enable the GIC CPU interface
104 *****************************************************************************/
105void plat_arm_gic_cpuif_enable(void)
106{
107 gicv3_cpuif_enable(plat_my_core_pos());
108}
109
110/******************************************************************************
111 * ARM common helper to disable the GIC CPU interface
112 *****************************************************************************/
113void plat_arm_gic_cpuif_disable(void)
114{
115 gicv3_cpuif_disable(plat_my_core_pos());
116}
117
118/******************************************************************************
119 * ARM common helper to initialize the per-cpu redistributor interface in GICv3
120 *****************************************************************************/
121void plat_arm_gic_pcpu_init(void)
122{
123 gicv3_rdistif_init(plat_my_core_pos());
124}
Jeenu Viswambharan78132c92016-12-09 11:12:34 +0000125
126/******************************************************************************
127 * ARM common helpers to power GIC redistributor interface
128 *****************************************************************************/
129void plat_arm_gic_redistif_on(void)
130{
131 gicv3_rdistif_on(plat_my_core_pos());
132}
133
134void plat_arm_gic_redistif_off(void)
135{
136 gicv3_rdistif_off(plat_my_core_pos());
137}
Soby Mathew9ca28062017-10-11 16:08:58 +0100138
139/******************************************************************************
140 * ARM common helper to save & restore the GICv3 on resume from system suspend
141 *****************************************************************************/
142void plat_arm_gic_save(void)
143{
Soby Mathew12cdcd22018-10-12 16:26:20 +0100144 gicv3_redist_ctx_t * const rdist_context =
145 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
146 gicv3_dist_ctx_t * const dist_context =
147 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
Soby Mathew9ca28062017-10-11 16:08:58 +0100148
149 /*
150 * If an ITS is available, save its context before
151 * the Redistributor using:
152 * gicv3_its_save_disable(gits_base, &its_ctx[i])
153 * Additionnaly, an implementation-defined sequence may
154 * be required to save the whole ITS state.
155 */
156
157 /*
158 * Save the GIC Redistributors and ITS contexts before the
159 * Distributor context. As we only handle SYSTEM SUSPEND API,
160 * we only need to save the context of the CPU that is issuing
161 * the SYSTEM SUSPEND call, i.e. the current CPU.
162 */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100163 gicv3_rdistif_save(plat_my_core_pos(), rdist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100164
165 /* Save the GIC Distributor context */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100166 gicv3_distif_save(dist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100167
168 /*
169 * From here, all the components of the GIC can be safely powered down
170 * as long as there is an alternate way to handle wakeup interrupt
171 * sources.
172 */
173}
174
175void plat_arm_gic_resume(void)
176{
Soby Mathew12cdcd22018-10-12 16:26:20 +0100177 const gicv3_redist_ctx_t *rdist_context =
178 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
179 const gicv3_dist_ctx_t *dist_context =
180 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
181
Soby Mathew9ca28062017-10-11 16:08:58 +0100182 /* Restore the GIC Distributor context */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100183 gicv3_distif_init_restore(dist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100184
185 /*
186 * Restore the GIC Redistributor and ITS contexts after the
187 * Distributor context. As we only handle SYSTEM SUSPEND API,
188 * we only need to restore the context of the CPU that issued
189 * the SYSTEM SUSPEND call.
190 */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100191 gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100192
193 /*
194 * If an ITS is available, restore its context after
195 * the Redistributor using:
196 * gicv3_its_restore(gits_base, &its_ctx[i])
197 * An implementation-defined sequence may be required to
198 * restore the whole ITS state. The ITS must also be
199 * re-enabled after this sequence has been executed.
200 */
201}