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Antonio Nino Diazae6779e2017-11-06 14:49:04 +00001/*
Antonio Nino Diaz6942f052018-07-14 02:15:51 +01002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Andre Przywarabb6ef152019-07-09 11:44:14 +01007#ifndef RPI_HW_H
8#define RPI_HW_H
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000011
12/*
13 * Peripherals
14 */
15
Andre Przywara4f4f7692019-07-09 15:59:26 +010016#define RPI_IO_BASE ULL(0x3F000000)
17#define RPI_IO_SIZE ULL(0x01000000)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000018
19/*
Antonio Nino Diazecf34712018-07-12 13:38:53 +010020 * ARM <-> VideoCore mailboxes
21 */
22#define RPI3_MBOX_OFFSET ULL(0x0000B880)
Andre Przywara4f4f7692019-07-09 15:59:26 +010023#define RPI3_MBOX_BASE (RPI_IO_BASE + RPI3_MBOX_OFFSET)
Antonio Nino Diazecf34712018-07-12 13:38:53 +010024/* VideoCore -> ARM */
25#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)
26#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)
27#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014)
28#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018)
29#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C)
30/* ARM -> VideoCore */
31#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020)
32#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030)
33#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034)
34#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038)
35#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C)
36/* Mailbox status constants */
37#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */
38#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */
39
40/*
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000041 * Power management, reset controller, watchdog.
42 */
43#define RPI3_IO_PM_OFFSET ULL(0x00100000)
Andre Przywara4f4f7692019-07-09 15:59:26 +010044#define RPI3_PM_BASE (RPI_IO_BASE + RPI3_IO_PM_OFFSET)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000045/* Registers on top of RPI3_PM_BASE. */
46#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C)
Antonio Nino Diaz6942f052018-07-14 02:15:51 +010047#define RPI3_PM_RSTS_OFFSET ULL(0x00000020)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000048#define RPI3_PM_WDOG_OFFSET ULL(0x00000024)
49/* Watchdog constants */
Antonio Nino Diaz6942f052018-07-14 02:15:51 +010050#define RPI3_PM_PASSWORD U(0x5A000000)
51#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030)
52#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020)
53/*
54 * The RSTS register is used by the VideoCore firmware when booting the
55 * Raspberry Pi to know which partition to boot from. The partition value is
56 * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware
57 * to indicate halt.
58 */
59#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555)
60
61/*
Antonio Nino Diaz12f73ff2018-07-13 09:27:16 +010062 * Hardware random number generator.
63 */
64#define RPI3_IO_RNG_OFFSET ULL(0x00104000)
Andre Przywara4f4f7692019-07-09 15:59:26 +010065#define RPI3_RNG_BASE (RPI_IO_BASE + RPI3_IO_RNG_OFFSET)
Antonio Nino Diaz12f73ff2018-07-13 09:27:16 +010066#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000)
67#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004)
68#define RPI3_RNG_DATA_OFFSET ULL(0x00000008)
69#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010)
70/* Enable/disable RNG */
71#define RPI3_RNG_CTRL_ENABLE U(0x1)
72#define RPI3_RNG_CTRL_DISABLE U(0x0)
73/* Number of currently available words */
74#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24)
75#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF)
76/* Value to mask interrupts caused by the RNG */
77#define RPI3_RNG_INT_MASK_DISABLE U(0x1)
78
79/*
Antonio Nino Diaz6942f052018-07-14 02:15:51 +010080 * Serial port (called 'Mini UART' in the BCM docucmentation).
81 */
82#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040)
Andre Przywara4f4f7692019-07-09 15:59:26 +010083#define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
Antonio Nino Diaz6942f052018-07-14 02:15:51 +010084#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000085
86/*
Ying-Chun Liu (PaulLiu)34527382019-01-22 03:27:55 +080087 * GPIO controller
88 */
89#define RPI3_IO_GPIO_OFFSET ULL(0x00200000)
Andre Przywara4f4f7692019-07-09 15:59:26 +010090#define RPI3_GPIO_BASE (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET)
Ying-Chun Liu (PaulLiu)34527382019-01-22 03:27:55 +080091
92/*
Ying-Chun Liu (PaulLiu)de6f2f42019-01-30 04:20:38 +080093 * SDHost controller
94 */
95#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000)
Andre Przywara4f4f7692019-07-09 15:59:26 +010096#define RPI3_SDHOST_BASE (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET)
Ying-Chun Liu (PaulLiu)de6f2f42019-01-30 04:20:38 +080097
98/*
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000099 * Local interrupt controller
100 */
101#define RPI3_INTC_BASE_ADDRESS ULL(0x40000000)
102/* Registers on top of RPI3_INTC_BASE_ADDRESS */
103#define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000)
104#define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008)
105#define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050)
106#define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080)
107#define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070)
108#define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080)
109
Andre Przywarabb6ef152019-07-09 11:44:14 +0100110#endif /* RPI_HW_H */