Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 1 | /* |
Yann Gautier | 8f268c8 | 2020-02-26 13:39:44 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Yann Gautier | e3bf913 | 2019-05-07 18:52:17 +0200 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | |
Yann Gautier | 35dc077 | 2019-05-13 18:34:48 +0200 | [diff] [blame] | 9 | #include <libfdt.h> |
| 10 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 11 | #include <platform_def.h> |
| 12 | |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 13 | #include <drivers/st/stm32_iwdg.h> |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 14 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 15 | |
Yann Gautier | 35dc077 | 2019-05-13 18:34:48 +0200 | [diff] [blame] | 16 | /* Internal layout of the 32bit OTP word board_id */ |
| 17 | #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) |
| 18 | #define BOARD_ID_BOARD_NB_SHIFT 16 |
| 19 | #define BOARD_ID_VARIANT_MASK GENMASK(15, 12) |
| 20 | #define BOARD_ID_VARIANT_SHIFT 12 |
| 21 | #define BOARD_ID_REVISION_MASK GENMASK(11, 8) |
| 22 | #define BOARD_ID_REVISION_SHIFT 8 |
| 23 | #define BOARD_ID_BOM_MASK GENMASK(3, 0) |
| 24 | |
| 25 | #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ |
| 26 | BOARD_ID_BOARD_NB_SHIFT) |
| 27 | #define BOARD_ID2VAR(_id) (((_id) & BOARD_ID_VARIANT_MASK) >> \ |
| 28 | BOARD_ID_VARIANT_SHIFT) |
| 29 | #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ |
| 30 | BOARD_ID_REVISION_SHIFT) |
| 31 | #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) |
| 32 | |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 33 | #if defined(IMAGE_BL2) |
| 34 | #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 35 | STM32MP_SYSRAM_SIZE, \ |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 36 | MT_MEMORY | \ |
| 37 | MT_RW | \ |
| 38 | MT_SECURE | \ |
| 39 | MT_EXECUTE_NEVER) |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 40 | #elif defined(IMAGE_BL32) |
| 41 | #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ |
| 42 | STM32MP_SEC_SYSRAM_SIZE, \ |
| 43 | MT_MEMORY | \ |
| 44 | MT_RW | \ |
| 45 | MT_SECURE | \ |
| 46 | MT_EXECUTE_NEVER) |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 47 | |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 48 | /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ |
| 49 | #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ |
| 50 | STM32MP_NS_SYSRAM_SIZE, \ |
| 51 | MT_DEVICE | \ |
| 52 | MT_RW | \ |
| 53 | MT_NS | \ |
| 54 | MT_EXECUTE_NEVER) |
| 55 | #endif |
| 56 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 57 | #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ |
| 58 | STM32MP1_DEVICE1_SIZE, \ |
| 59 | MT_DEVICE | \ |
| 60 | MT_RW | \ |
| 61 | MT_SECURE | \ |
| 62 | MT_EXECUTE_NEVER) |
| 63 | |
| 64 | #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ |
| 65 | STM32MP1_DEVICE2_SIZE, \ |
| 66 | MT_DEVICE | \ |
| 67 | MT_RW | \ |
| 68 | MT_SECURE | \ |
| 69 | MT_EXECUTE_NEVER) |
| 70 | |
| 71 | #if defined(IMAGE_BL2) |
| 72 | static const mmap_region_t stm32mp1_mmap[] = { |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 73 | MAP_SEC_SYSRAM, |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 74 | MAP_DEVICE1, |
| 75 | MAP_DEVICE2, |
| 76 | {0} |
| 77 | }; |
| 78 | #endif |
| 79 | #if defined(IMAGE_BL32) |
| 80 | static const mmap_region_t stm32mp1_mmap[] = { |
Etienne Carriere | 72369b1 | 2019-12-08 08:17:56 +0100 | [diff] [blame] | 81 | MAP_SEC_SYSRAM, |
| 82 | MAP_NS_SYSRAM, |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 83 | MAP_DEVICE1, |
| 84 | MAP_DEVICE2, |
| 85 | {0} |
| 86 | }; |
| 87 | #endif |
| 88 | |
| 89 | void configure_mmu(void) |
| 90 | { |
| 91 | mmap_add(stm32mp1_mmap); |
| 92 | init_xlat_tables(); |
| 93 | |
| 94 | enable_mmu_svc_mon(0); |
| 95 | } |
Yann Gautier | e3bf913 | 2019-05-07 18:52:17 +0200 | [diff] [blame] | 96 | |
Etienne Carriere | 66b0452 | 2019-12-02 10:05:02 +0100 | [diff] [blame] | 97 | uintptr_t stm32_get_gpio_bank_base(unsigned int bank) |
| 98 | { |
| 99 | if (bank == GPIO_BANK_Z) { |
| 100 | return GPIOZ_BASE; |
| 101 | } |
| 102 | |
| 103 | assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); |
| 104 | |
| 105 | return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); |
| 106 | } |
| 107 | |
| 108 | uint32_t stm32_get_gpio_bank_offset(unsigned int bank) |
| 109 | { |
| 110 | if (bank == GPIO_BANK_Z) { |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); |
| 115 | |
| 116 | return bank * GPIO_BANK_OFFSET; |
| 117 | } |
| 118 | |
Yann Gautier | e3bf913 | 2019-05-07 18:52:17 +0200 | [diff] [blame] | 119 | unsigned long stm32_get_gpio_bank_clock(unsigned int bank) |
| 120 | { |
| 121 | if (bank == GPIO_BANK_Z) { |
| 122 | return GPIOZ; |
| 123 | } |
| 124 | |
| 125 | assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); |
| 126 | |
| 127 | return GPIOA + (bank - GPIO_BANK_A); |
| 128 | } |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 129 | |
Etienne Carriere | d81dadf | 2020-04-25 11:14:45 +0200 | [diff] [blame] | 130 | int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) |
| 131 | { |
| 132 | switch (bank) { |
| 133 | case GPIO_BANK_A: |
| 134 | case GPIO_BANK_B: |
| 135 | case GPIO_BANK_C: |
| 136 | case GPIO_BANK_D: |
| 137 | case GPIO_BANK_E: |
| 138 | case GPIO_BANK_F: |
| 139 | case GPIO_BANK_G: |
| 140 | case GPIO_BANK_H: |
| 141 | case GPIO_BANK_I: |
| 142 | case GPIO_BANK_J: |
| 143 | case GPIO_BANK_K: |
| 144 | return fdt_path_offset(fdt, "/soc/pin-controller"); |
| 145 | case GPIO_BANK_Z: |
| 146 | return fdt_path_offset(fdt, "/soc/pin-controller-z"); |
| 147 | default: |
| 148 | panic(); |
| 149 | } |
| 150 | } |
| 151 | |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 152 | static int get_part_number(uint32_t *part_nb) |
| 153 | { |
| 154 | uint32_t part_number; |
| 155 | uint32_t dev_id; |
| 156 | |
| 157 | if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { |
| 158 | return -1; |
| 159 | } |
| 160 | |
| 161 | if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { |
| 162 | ERROR("BSEC: PART_NUMBER_OTP Error\n"); |
| 163 | return -1; |
| 164 | } |
| 165 | |
| 166 | part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> |
| 167 | PART_NUMBER_OTP_PART_SHIFT; |
| 168 | |
| 169 | *part_nb = part_number | (dev_id << 16); |
| 170 | |
| 171 | return 0; |
| 172 | } |
| 173 | |
| 174 | static int get_cpu_package(uint32_t *cpu_package) |
| 175 | { |
| 176 | uint32_t package; |
| 177 | |
| 178 | if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { |
| 179 | ERROR("BSEC: PACKAGE_OTP Error\n"); |
| 180 | return -1; |
| 181 | } |
| 182 | |
| 183 | *cpu_package = (package & PACKAGE_OTP_PKG_MASK) >> |
| 184 | PACKAGE_OTP_PKG_SHIFT; |
| 185 | |
| 186 | return 0; |
| 187 | } |
| 188 | |
| 189 | void stm32mp_print_cpuinfo(void) |
| 190 | { |
| 191 | const char *cpu_s, *cpu_r, *pkg; |
| 192 | uint32_t part_number; |
| 193 | uint32_t cpu_package; |
| 194 | uint32_t chip_dev_id; |
| 195 | int ret; |
| 196 | |
| 197 | /* MPUs Part Numbers */ |
| 198 | ret = get_part_number(&part_number); |
| 199 | if (ret < 0) { |
| 200 | WARN("Cannot get part number\n"); |
| 201 | return; |
| 202 | } |
| 203 | |
| 204 | switch (part_number) { |
| 205 | case STM32MP157C_PART_NB: |
| 206 | cpu_s = "157C"; |
| 207 | break; |
| 208 | case STM32MP157A_PART_NB: |
| 209 | cpu_s = "157A"; |
| 210 | break; |
| 211 | case STM32MP153C_PART_NB: |
| 212 | cpu_s = "153C"; |
| 213 | break; |
| 214 | case STM32MP153A_PART_NB: |
| 215 | cpu_s = "153A"; |
| 216 | break; |
| 217 | case STM32MP151C_PART_NB: |
| 218 | cpu_s = "151C"; |
| 219 | break; |
| 220 | case STM32MP151A_PART_NB: |
| 221 | cpu_s = "151A"; |
| 222 | break; |
Lionel Debieve | 7b64e3e | 2019-05-17 16:01:18 +0200 | [diff] [blame] | 223 | case STM32MP157F_PART_NB: |
| 224 | cpu_s = "157F"; |
| 225 | break; |
| 226 | case STM32MP157D_PART_NB: |
| 227 | cpu_s = "157D"; |
| 228 | break; |
| 229 | case STM32MP153F_PART_NB: |
| 230 | cpu_s = "153F"; |
| 231 | break; |
| 232 | case STM32MP153D_PART_NB: |
| 233 | cpu_s = "153D"; |
| 234 | break; |
| 235 | case STM32MP151F_PART_NB: |
| 236 | cpu_s = "151F"; |
| 237 | break; |
| 238 | case STM32MP151D_PART_NB: |
| 239 | cpu_s = "151D"; |
| 240 | break; |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 241 | default: |
| 242 | cpu_s = "????"; |
| 243 | break; |
| 244 | } |
| 245 | |
| 246 | /* Package */ |
| 247 | ret = get_cpu_package(&cpu_package); |
| 248 | if (ret < 0) { |
| 249 | WARN("Cannot get CPU package\n"); |
| 250 | return; |
| 251 | } |
| 252 | |
| 253 | switch (cpu_package) { |
| 254 | case PKG_AA_LFBGA448: |
| 255 | pkg = "AA"; |
| 256 | break; |
| 257 | case PKG_AB_LFBGA354: |
| 258 | pkg = "AB"; |
| 259 | break; |
| 260 | case PKG_AC_TFBGA361: |
| 261 | pkg = "AC"; |
| 262 | break; |
| 263 | case PKG_AD_TFBGA257: |
| 264 | pkg = "AD"; |
| 265 | break; |
| 266 | default: |
| 267 | pkg = "??"; |
| 268 | break; |
| 269 | } |
| 270 | |
| 271 | /* REVISION */ |
| 272 | ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id); |
| 273 | if (ret < 0) { |
| 274 | WARN("Cannot get CPU version\n"); |
| 275 | return; |
| 276 | } |
| 277 | |
| 278 | switch (chip_dev_id) { |
| 279 | case STM32MP1_REV_B: |
| 280 | cpu_r = "B"; |
| 281 | break; |
Lionel Debieve | 2d64b53 | 2019-06-25 10:40:37 +0200 | [diff] [blame] | 282 | case STM32MP1_REV_Z: |
| 283 | cpu_r = "Z"; |
| 284 | break; |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 285 | default: |
| 286 | cpu_r = "?"; |
| 287 | break; |
| 288 | } |
| 289 | |
| 290 | NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r); |
| 291 | } |
| 292 | |
Yann Gautier | 35dc077 | 2019-05-13 18:34:48 +0200 | [diff] [blame] | 293 | void stm32mp_print_boardinfo(void) |
| 294 | { |
| 295 | uint32_t board_id; |
| 296 | uint32_t board_otp; |
| 297 | int bsec_node, bsec_board_id_node; |
| 298 | void *fdt; |
| 299 | const fdt32_t *cuint; |
| 300 | |
| 301 | if (fdt_get_address(&fdt) == 0) { |
| 302 | panic(); |
| 303 | } |
| 304 | |
| 305 | bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT); |
| 306 | if (bsec_node < 0) { |
| 307 | return; |
| 308 | } |
| 309 | |
| 310 | bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id"); |
| 311 | if (bsec_board_id_node <= 0) { |
| 312 | return; |
| 313 | } |
| 314 | |
| 315 | cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL); |
| 316 | if (cuint == NULL) { |
| 317 | panic(); |
| 318 | } |
| 319 | |
| 320 | board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t); |
| 321 | |
| 322 | if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) { |
| 323 | ERROR("BSEC: PART_NUMBER_OTP Error\n"); |
| 324 | return; |
| 325 | } |
| 326 | |
| 327 | if (board_id != 0U) { |
| 328 | char rev[2]; |
| 329 | |
| 330 | rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; |
| 331 | rev[1] = '\0'; |
| 332 | NOTICE("Board: MB%04x Var%d Rev.%s-%02d\n", |
| 333 | BOARD_ID2NB(board_id), |
| 334 | BOARD_ID2VAR(board_id), |
| 335 | rev, |
| 336 | BOARD_ID2BOM(board_id)); |
| 337 | } |
| 338 | } |
| 339 | |
Yann Gautier | af19ff9 | 2019-06-04 18:23:10 +0200 | [diff] [blame] | 340 | /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ |
| 341 | bool stm32mp_is_single_core(void) |
| 342 | { |
| 343 | uint32_t part_number; |
Yann Gautier | af19ff9 | 2019-06-04 18:23:10 +0200 | [diff] [blame] | 344 | |
| 345 | if (get_part_number(&part_number) < 0) { |
| 346 | ERROR("Invalid part number, assume single core chip"); |
| 347 | return true; |
| 348 | } |
| 349 | |
| 350 | switch (part_number) { |
| 351 | case STM32MP151A_PART_NB: |
| 352 | case STM32MP151C_PART_NB: |
Lionel Debieve | 7b64e3e | 2019-05-17 16:01:18 +0200 | [diff] [blame] | 353 | case STM32MP151D_PART_NB: |
| 354 | case STM32MP151F_PART_NB: |
| 355 | return true; |
Yann Gautier | af19ff9 | 2019-06-04 18:23:10 +0200 | [diff] [blame] | 356 | |
| 357 | default: |
Lionel Debieve | 7b64e3e | 2019-05-17 16:01:18 +0200 | [diff] [blame] | 358 | return false; |
Yann Gautier | af19ff9 | 2019-06-04 18:23:10 +0200 | [diff] [blame] | 359 | } |
Yann Gautier | af19ff9 | 2019-06-04 18:23:10 +0200 | [diff] [blame] | 360 | } |
| 361 | |
Lionel Debieve | 0e73d73 | 2019-09-16 12:17:09 +0200 | [diff] [blame] | 362 | /* Return true when device is in closed state */ |
| 363 | bool stm32mp_is_closed_device(void) |
| 364 | { |
| 365 | uint32_t value; |
| 366 | |
| 367 | if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) || |
| 368 | (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) { |
| 369 | return true; |
| 370 | } |
| 371 | |
| 372 | return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED; |
| 373 | } |
| 374 | |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 375 | uint32_t stm32_iwdg_get_instance(uintptr_t base) |
| 376 | { |
| 377 | switch (base) { |
| 378 | case IWDG1_BASE: |
| 379 | return IWDG1_INST; |
| 380 | case IWDG2_BASE: |
| 381 | return IWDG2_INST; |
| 382 | default: |
| 383 | panic(); |
| 384 | } |
| 385 | } |
| 386 | |
| 387 | uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) |
| 388 | { |
| 389 | uint32_t iwdg_cfg = 0U; |
| 390 | uint32_t otp_value; |
| 391 | |
| 392 | #if defined(IMAGE_BL2) |
| 393 | if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { |
| 394 | panic(); |
| 395 | } |
| 396 | #endif |
| 397 | |
| 398 | if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { |
| 399 | panic(); |
| 400 | } |
| 401 | |
| 402 | if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { |
| 403 | iwdg_cfg |= IWDG_HW_ENABLED; |
| 404 | } |
| 405 | |
| 406 | if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { |
| 407 | iwdg_cfg |= IWDG_DISABLE_ON_STOP; |
| 408 | } |
| 409 | |
| 410 | if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { |
| 411 | iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; |
| 412 | } |
| 413 | |
| 414 | return iwdg_cfg; |
| 415 | } |
| 416 | |
| 417 | #if defined(IMAGE_BL2) |
| 418 | uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) |
| 419 | { |
| 420 | uint32_t otp; |
| 421 | uint32_t result; |
| 422 | |
| 423 | if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { |
| 424 | panic(); |
| 425 | } |
| 426 | |
| 427 | if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { |
| 428 | otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); |
| 429 | } |
| 430 | |
| 431 | if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { |
| 432 | otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); |
| 433 | } |
| 434 | |
| 435 | result = bsec_write_otp(otp, HW2_OTP); |
| 436 | if (result != BSEC_OK) { |
| 437 | return result; |
| 438 | } |
| 439 | |
| 440 | /* Sticky lock OTP_IWDG (read and write) */ |
| 441 | if (!bsec_write_sr_lock(HW2_OTP, 1U) || |
| 442 | !bsec_write_sw_lock(HW2_OTP, 1U)) { |
| 443 | return BSEC_LOCK_FAIL; |
| 444 | } |
| 445 | |
| 446 | return BSEC_OK; |
| 447 | } |
| 448 | #endif |
Yann Gautier | 8f268c8 | 2020-02-26 13:39:44 +0100 | [diff] [blame] | 449 | |
| 450 | /* Get the non-secure DDR size */ |
| 451 | uint32_t stm32mp_get_ddr_ns_size(void) |
| 452 | { |
| 453 | static uint32_t ddr_ns_size; |
| 454 | uint32_t ddr_size; |
| 455 | |
| 456 | if (ddr_ns_size != 0U) { |
| 457 | return ddr_ns_size; |
| 458 | } |
| 459 | |
| 460 | ddr_size = dt_get_ddr_size(); |
| 461 | if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || |
| 462 | (ddr_size > STM32MP_DDR_MAX_SIZE)) { |
| 463 | panic(); |
| 464 | } |
| 465 | |
| 466 | ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); |
| 467 | |
| 468 | return ddr_ns_size; |
| 469 | } |