Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Yann Gautier | e3bf913 | 2019-05-07 18:52:17 +0200 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 9 | #include <platform_def.h> |
| 10 | |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 11 | #include <drivers/st/stm32_iwdg.h> |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 12 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 13 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 14 | #define MAP_SRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ |
| 15 | STM32MP_SYSRAM_SIZE, \ |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 16 | MT_MEMORY | \ |
| 17 | MT_RW | \ |
| 18 | MT_SECURE | \ |
| 19 | MT_EXECUTE_NEVER) |
| 20 | |
| 21 | #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ |
| 22 | STM32MP1_DEVICE1_SIZE, \ |
| 23 | MT_DEVICE | \ |
| 24 | MT_RW | \ |
| 25 | MT_SECURE | \ |
| 26 | MT_EXECUTE_NEVER) |
| 27 | |
| 28 | #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ |
| 29 | STM32MP1_DEVICE2_SIZE, \ |
| 30 | MT_DEVICE | \ |
| 31 | MT_RW | \ |
| 32 | MT_SECURE | \ |
| 33 | MT_EXECUTE_NEVER) |
| 34 | |
| 35 | #if defined(IMAGE_BL2) |
| 36 | static const mmap_region_t stm32mp1_mmap[] = { |
| 37 | MAP_SRAM, |
| 38 | MAP_DEVICE1, |
| 39 | MAP_DEVICE2, |
| 40 | {0} |
| 41 | }; |
| 42 | #endif |
| 43 | #if defined(IMAGE_BL32) |
| 44 | static const mmap_region_t stm32mp1_mmap[] = { |
| 45 | MAP_SRAM, |
| 46 | MAP_DEVICE1, |
| 47 | MAP_DEVICE2, |
| 48 | {0} |
| 49 | }; |
| 50 | #endif |
| 51 | |
| 52 | void configure_mmu(void) |
| 53 | { |
| 54 | mmap_add(stm32mp1_mmap); |
| 55 | init_xlat_tables(); |
| 56 | |
| 57 | enable_mmu_svc_mon(0); |
| 58 | } |
Yann Gautier | e3bf913 | 2019-05-07 18:52:17 +0200 | [diff] [blame] | 59 | |
| 60 | unsigned long stm32_get_gpio_bank_clock(unsigned int bank) |
| 61 | { |
| 62 | if (bank == GPIO_BANK_Z) { |
| 63 | return GPIOZ; |
| 64 | } |
| 65 | |
| 66 | assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); |
| 67 | |
| 68 | return GPIOA + (bank - GPIO_BANK_A); |
| 69 | } |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 70 | |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame^] | 71 | static int get_part_number(uint32_t *part_nb) |
| 72 | { |
| 73 | uint32_t part_number; |
| 74 | uint32_t dev_id; |
| 75 | |
| 76 | if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { |
| 77 | return -1; |
| 78 | } |
| 79 | |
| 80 | if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { |
| 81 | ERROR("BSEC: PART_NUMBER_OTP Error\n"); |
| 82 | return -1; |
| 83 | } |
| 84 | |
| 85 | part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> |
| 86 | PART_NUMBER_OTP_PART_SHIFT; |
| 87 | |
| 88 | *part_nb = part_number | (dev_id << 16); |
| 89 | |
| 90 | return 0; |
| 91 | } |
| 92 | |
| 93 | static int get_cpu_package(uint32_t *cpu_package) |
| 94 | { |
| 95 | uint32_t package; |
| 96 | |
| 97 | if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { |
| 98 | ERROR("BSEC: PACKAGE_OTP Error\n"); |
| 99 | return -1; |
| 100 | } |
| 101 | |
| 102 | *cpu_package = (package & PACKAGE_OTP_PKG_MASK) >> |
| 103 | PACKAGE_OTP_PKG_SHIFT; |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | void stm32mp_print_cpuinfo(void) |
| 109 | { |
| 110 | const char *cpu_s, *cpu_r, *pkg; |
| 111 | uint32_t part_number; |
| 112 | uint32_t cpu_package; |
| 113 | uint32_t chip_dev_id; |
| 114 | int ret; |
| 115 | |
| 116 | /* MPUs Part Numbers */ |
| 117 | ret = get_part_number(&part_number); |
| 118 | if (ret < 0) { |
| 119 | WARN("Cannot get part number\n"); |
| 120 | return; |
| 121 | } |
| 122 | |
| 123 | switch (part_number) { |
| 124 | case STM32MP157C_PART_NB: |
| 125 | cpu_s = "157C"; |
| 126 | break; |
| 127 | case STM32MP157A_PART_NB: |
| 128 | cpu_s = "157A"; |
| 129 | break; |
| 130 | case STM32MP153C_PART_NB: |
| 131 | cpu_s = "153C"; |
| 132 | break; |
| 133 | case STM32MP153A_PART_NB: |
| 134 | cpu_s = "153A"; |
| 135 | break; |
| 136 | case STM32MP151C_PART_NB: |
| 137 | cpu_s = "151C"; |
| 138 | break; |
| 139 | case STM32MP151A_PART_NB: |
| 140 | cpu_s = "151A"; |
| 141 | break; |
| 142 | default: |
| 143 | cpu_s = "????"; |
| 144 | break; |
| 145 | } |
| 146 | |
| 147 | /* Package */ |
| 148 | ret = get_cpu_package(&cpu_package); |
| 149 | if (ret < 0) { |
| 150 | WARN("Cannot get CPU package\n"); |
| 151 | return; |
| 152 | } |
| 153 | |
| 154 | switch (cpu_package) { |
| 155 | case PKG_AA_LFBGA448: |
| 156 | pkg = "AA"; |
| 157 | break; |
| 158 | case PKG_AB_LFBGA354: |
| 159 | pkg = "AB"; |
| 160 | break; |
| 161 | case PKG_AC_TFBGA361: |
| 162 | pkg = "AC"; |
| 163 | break; |
| 164 | case PKG_AD_TFBGA257: |
| 165 | pkg = "AD"; |
| 166 | break; |
| 167 | default: |
| 168 | pkg = "??"; |
| 169 | break; |
| 170 | } |
| 171 | |
| 172 | /* REVISION */ |
| 173 | ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id); |
| 174 | if (ret < 0) { |
| 175 | WARN("Cannot get CPU version\n"); |
| 176 | return; |
| 177 | } |
| 178 | |
| 179 | switch (chip_dev_id) { |
| 180 | case STM32MP1_REV_B: |
| 181 | cpu_r = "B"; |
| 182 | break; |
| 183 | default: |
| 184 | cpu_r = "?"; |
| 185 | break; |
| 186 | } |
| 187 | |
| 188 | NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r); |
| 189 | } |
| 190 | |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 191 | uint32_t stm32_iwdg_get_instance(uintptr_t base) |
| 192 | { |
| 193 | switch (base) { |
| 194 | case IWDG1_BASE: |
| 195 | return IWDG1_INST; |
| 196 | case IWDG2_BASE: |
| 197 | return IWDG2_INST; |
| 198 | default: |
| 199 | panic(); |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) |
| 204 | { |
| 205 | uint32_t iwdg_cfg = 0U; |
| 206 | uint32_t otp_value; |
| 207 | |
| 208 | #if defined(IMAGE_BL2) |
| 209 | if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { |
| 210 | panic(); |
| 211 | } |
| 212 | #endif |
| 213 | |
| 214 | if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { |
| 215 | panic(); |
| 216 | } |
| 217 | |
| 218 | if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { |
| 219 | iwdg_cfg |= IWDG_HW_ENABLED; |
| 220 | } |
| 221 | |
| 222 | if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { |
| 223 | iwdg_cfg |= IWDG_DISABLE_ON_STOP; |
| 224 | } |
| 225 | |
| 226 | if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { |
| 227 | iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; |
| 228 | } |
| 229 | |
| 230 | return iwdg_cfg; |
| 231 | } |
| 232 | |
| 233 | #if defined(IMAGE_BL2) |
| 234 | uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) |
| 235 | { |
| 236 | uint32_t otp; |
| 237 | uint32_t result; |
| 238 | |
| 239 | if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { |
| 240 | panic(); |
| 241 | } |
| 242 | |
| 243 | if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { |
| 244 | otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); |
| 245 | } |
| 246 | |
| 247 | if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { |
| 248 | otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); |
| 249 | } |
| 250 | |
| 251 | result = bsec_write_otp(otp, HW2_OTP); |
| 252 | if (result != BSEC_OK) { |
| 253 | return result; |
| 254 | } |
| 255 | |
| 256 | /* Sticky lock OTP_IWDG (read and write) */ |
| 257 | if (!bsec_write_sr_lock(HW2_OTP, 1U) || |
| 258 | !bsec_write_sw_lock(HW2_OTP, 1U)) { |
| 259 | return BSEC_LOCK_FAIL; |
| 260 | } |
| 261 | |
| 262 | return BSEC_OK; |
| 263 | } |
| 264 | #endif |