Blame - bl32/tsp/aarch64/tsp_exceptions.S - filogic/atf

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Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	1	/*
Antonio Nino Diaz	1f21bcf	2016-02-01 13:57:25 +0000	[diff] [blame]	2	* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	3	*
dp-arm	fa3cf0b	2017-05-03 09:38:09 +0100	[diff] [blame]	4	* SPDX-License-Identifier: BSD-3-Clause
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	5	*/
				6
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	7	#include <arch.h>
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	8	#include <asm_macros.S>
Antonio Nino Diaz	e0f9063	2018-12-14 00:18:21 +0000	[diff] [blame]	9	#include <bl32/tsp/tsp.h>
				10	#include <common/bl_common.h>
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	11
				12	/* ----------------------------------------------------
				13	* The caller-saved registers x0-x18 and LR are saved
				14	* here.
				15	* ----------------------------------------------------
				16	*/
				17
				18	#define SCRATCH_REG_SIZE #(20 * 8)
				19
				20	.macro save_caller_regs_and_lr
				21	sub sp, sp, SCRATCH_REG_SIZE
				22	stp x0, x1, [sp]
				23	stp x2, x3, [sp, #0x10]
				24	stp x4, x5, [sp, #0x20]
				25	stp x6, x7, [sp, #0x30]
				26	stp x8, x9, [sp, #0x40]
				27	stp x10, x11, [sp, #0x50]
				28	stp x12, x13, [sp, #0x60]
				29	stp x14, x15, [sp, #0x70]
				30	stp x16, x17, [sp, #0x80]
				31	stp x18, x30, [sp, #0x90]
				32	.endm
				33
				34	.macro restore_caller_regs_and_lr
				35	ldp x0, x1, [sp]
				36	ldp x2, x3, [sp, #0x10]
				37	ldp x4, x5, [sp, #0x20]
				38	ldp x6, x7, [sp, #0x30]
				39	ldp x8, x9, [sp, #0x40]
				40	ldp x10, x11, [sp, #0x50]
				41	ldp x12, x13, [sp, #0x60]
				42	ldp x14, x15, [sp, #0x70]
				43	ldp x16, x17, [sp, #0x80]
				44	ldp x18, x30, [sp, #0x90]
				45	add sp, sp, SCRATCH_REG_SIZE
				46	.endm
				47
Soby Mathew	bec9851	2015-09-03 18:29:38 +0100	[diff] [blame]	48	/* ----------------------------------------------------
				49	* Common TSP interrupt handling routine
				50	* ----------------------------------------------------
				51	*/
				52	.macro handle_tsp_interrupt label
				53	/* Enable the SError interrupt */
				54	msr daifclr, #DAIF_ABT_BIT
				55
				56	save_caller_regs_and_lr
				57	bl tsp_common_int_handler
				58	cbz x0, interrupt_exit_\label
				59
				60	/*
				61	* This interrupt was not targetted to S-EL1 so send it to
				62	* the monitor and wait for execution to resume.
				63	*/
				64	smc #0
				65	interrupt_exit_\label:
				66	restore_caller_regs_and_lr
				67	eret
				68	.endm
				69
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	70	.globl tsp_exceptions
				71
				72	/* -----------------------------------------------------
				73	* TSP exception handlers.
				74	* -----------------------------------------------------
				75	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	76	vector_base tsp_exceptions
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	77	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	78	* Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	79	* are expected and treated as irrecoverable errors.
				80	* -----------------------------------------------------
				81	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	82	vector_entry sync_exception_sp_el0
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	83	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	84	end_vector_entry sync_exception_sp_el0
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	85
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	86	vector_entry irq_sp_el0
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	87	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	88	end_vector_entry irq_sp_el0
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	89
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	90	vector_entry fiq_sp_el0
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	91	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	92	end_vector_entry fiq_sp_el0
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	93
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	94	vector_entry serror_sp_el0
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	95	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	96	end_vector_entry serror_sp_el0
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	97
				98
				99	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	100	* Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	101	* are expected and handled
				102	* -----------------------------------------------------
				103	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	104	vector_entry sync_exception_sp_elx
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	105	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	106	end_vector_entry sync_exception_sp_elx
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	107
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	108	vector_entry irq_sp_elx
Soby Mathew	bec9851	2015-09-03 18:29:38 +0100	[diff] [blame]	109	handle_tsp_interrupt irq_sp_elx
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	110	end_vector_entry irq_sp_elx
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	111
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	112	vector_entry fiq_sp_elx
Soby Mathew	bec9851	2015-09-03 18:29:38 +0100	[diff] [blame]	113	handle_tsp_interrupt fiq_sp_elx
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	114	end_vector_entry fiq_sp_elx
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	115
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	116	vector_entry serror_sp_elx
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	117	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	118	end_vector_entry serror_sp_elx
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	119
				120
				121	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	122	* Lower EL using AArch64 : 0x400 - 0x600. No exceptions
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	123	* are handled since TSP does not implement a lower EL
				124	* -----------------------------------------------------
				125	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	126	vector_entry sync_exception_aarch64
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	127	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	128	end_vector_entry sync_exception_aarch64
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	129
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	130	vector_entry irq_aarch64
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	131	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	132	end_vector_entry irq_aarch64
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	133
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	134	vector_entry fiq_aarch64
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	135	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	136	end_vector_entry fiq_aarch64
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	137
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	138	vector_entry serror_aarch64
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	139	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	140	end_vector_entry serror_aarch64
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	141
				142
				143	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	144	* Lower EL using AArch32 : 0x600 - 0x800. No exceptions
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	145	* handled since the TSP does not implement a lower EL.
				146	* -----------------------------------------------------
				147	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	148	vector_entry sync_exception_aarch32
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	149	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	150	end_vector_entry sync_exception_aarch32
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	151
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	152	vector_entry irq_aarch32
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	153	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	154	end_vector_entry irq_aarch32
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	155
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	156	vector_entry fiq_aarch32
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	157	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	158	end_vector_entry fiq_aarch32
Achin Gupta	a4f50c2	2014-05-09 12:17:56 +0100	[diff] [blame]	159
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	160	vector_entry serror_aarch32
Julius Werner	67ebde7	2017-07-27 14:59:34 -0700	[diff] [blame]	161	b plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	162	end_vector_entry serror_aarch32