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Achin Guptaa4f50c22014-05-09 12:17:56 +01001/*
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Guptaa4f50c22014-05-09 12:17:56 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Guptaa4f50c22014-05-09 12:17:56 +01005 */
6
Achin Guptaa4f50c22014-05-09 12:17:56 +01007#include <arch.h>
Achin Guptaa4f50c22014-05-09 12:17:56 +01008#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <bl32/tsp/tsp.h>
10#include <common/bl_common.h>
Achin Guptaa4f50c22014-05-09 12:17:56 +010011
12 /* ----------------------------------------------------
13 * The caller-saved registers x0-x18 and LR are saved
14 * here.
15 * ----------------------------------------------------
16 */
17
18#define SCRATCH_REG_SIZE #(20 * 8)
19
20 .macro save_caller_regs_and_lr
21 sub sp, sp, SCRATCH_REG_SIZE
22 stp x0, x1, [sp]
23 stp x2, x3, [sp, #0x10]
24 stp x4, x5, [sp, #0x20]
25 stp x6, x7, [sp, #0x30]
26 stp x8, x9, [sp, #0x40]
27 stp x10, x11, [sp, #0x50]
28 stp x12, x13, [sp, #0x60]
29 stp x14, x15, [sp, #0x70]
30 stp x16, x17, [sp, #0x80]
31 stp x18, x30, [sp, #0x90]
32 .endm
33
34 .macro restore_caller_regs_and_lr
35 ldp x0, x1, [sp]
36 ldp x2, x3, [sp, #0x10]
37 ldp x4, x5, [sp, #0x20]
38 ldp x6, x7, [sp, #0x30]
39 ldp x8, x9, [sp, #0x40]
40 ldp x10, x11, [sp, #0x50]
41 ldp x12, x13, [sp, #0x60]
42 ldp x14, x15, [sp, #0x70]
43 ldp x16, x17, [sp, #0x80]
44 ldp x18, x30, [sp, #0x90]
45 add sp, sp, SCRATCH_REG_SIZE
46 .endm
47
Soby Mathewbec98512015-09-03 18:29:38 +010048 /* ----------------------------------------------------
49 * Common TSP interrupt handling routine
50 * ----------------------------------------------------
51 */
52 .macro handle_tsp_interrupt label
53 /* Enable the SError interrupt */
54 msr daifclr, #DAIF_ABT_BIT
55
56 save_caller_regs_and_lr
57 bl tsp_common_int_handler
58 cbz x0, interrupt_exit_\label
59
60 /*
61 * This interrupt was not targetted to S-EL1 so send it to
62 * the monitor and wait for execution to resume.
63 */
64 smc #0
65interrupt_exit_\label:
66 restore_caller_regs_and_lr
67 eret
68 .endm
69
Achin Guptaa4f50c22014-05-09 12:17:56 +010070 .globl tsp_exceptions
71
72 /* -----------------------------------------------------
73 * TSP exception handlers.
74 * -----------------------------------------------------
75 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010076vector_base tsp_exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +010077 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010078 * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +010079 * are expected and treated as irrecoverable errors.
80 * -----------------------------------------------------
81 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010082vector_entry sync_exception_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -070083 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010084end_vector_entry sync_exception_sp_el0
Achin Guptaa4f50c22014-05-09 12:17:56 +010085
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010086vector_entry irq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -070087 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010088end_vector_entry irq_sp_el0
Achin Guptaa4f50c22014-05-09 12:17:56 +010089
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010090vector_entry fiq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -070091 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010092end_vector_entry fiq_sp_el0
Achin Guptaa4f50c22014-05-09 12:17:56 +010093
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010094vector_entry serror_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -070095 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010096end_vector_entry serror_sp_el0
Achin Guptaa4f50c22014-05-09 12:17:56 +010097
98
99 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100100 * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
Achin Guptaa4f50c22014-05-09 12:17:56 +0100101 * are expected and handled
102 * -----------------------------------------------------
103 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100104vector_entry sync_exception_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700105 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100106end_vector_entry sync_exception_sp_elx
Achin Guptaa4f50c22014-05-09 12:17:56 +0100107
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100108vector_entry irq_sp_elx
Soby Mathewbec98512015-09-03 18:29:38 +0100109 handle_tsp_interrupt irq_sp_elx
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100110end_vector_entry irq_sp_elx
Achin Guptaa4f50c22014-05-09 12:17:56 +0100111
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100112vector_entry fiq_sp_elx
Soby Mathewbec98512015-09-03 18:29:38 +0100113 handle_tsp_interrupt fiq_sp_elx
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100114end_vector_entry fiq_sp_elx
Achin Guptaa4f50c22014-05-09 12:17:56 +0100115
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100116vector_entry serror_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700117 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100118end_vector_entry serror_sp_elx
Achin Guptaa4f50c22014-05-09 12:17:56 +0100119
120
121 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100122 * Lower EL using AArch64 : 0x400 - 0x600. No exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +0100123 * are handled since TSP does not implement a lower EL
124 * -----------------------------------------------------
125 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100126vector_entry sync_exception_aarch64
Julius Werner67ebde72017-07-27 14:59:34 -0700127 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100128end_vector_entry sync_exception_aarch64
Achin Guptaa4f50c22014-05-09 12:17:56 +0100129
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100130vector_entry irq_aarch64
Julius Werner67ebde72017-07-27 14:59:34 -0700131 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100132end_vector_entry irq_aarch64
Achin Guptaa4f50c22014-05-09 12:17:56 +0100133
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100134vector_entry fiq_aarch64
Julius Werner67ebde72017-07-27 14:59:34 -0700135 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100136end_vector_entry fiq_aarch64
Achin Guptaa4f50c22014-05-09 12:17:56 +0100137
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100138vector_entry serror_aarch64
Julius Werner67ebde72017-07-27 14:59:34 -0700139 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100140end_vector_entry serror_aarch64
Achin Guptaa4f50c22014-05-09 12:17:56 +0100141
142
143 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100144 * Lower EL using AArch32 : 0x600 - 0x800. No exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +0100145 * handled since the TSP does not implement a lower EL.
146 * -----------------------------------------------------
147 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100148vector_entry sync_exception_aarch32
Julius Werner67ebde72017-07-27 14:59:34 -0700149 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100150end_vector_entry sync_exception_aarch32
Achin Guptaa4f50c22014-05-09 12:17:56 +0100151
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100152vector_entry irq_aarch32
Julius Werner67ebde72017-07-27 14:59:34 -0700153 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100154end_vector_entry irq_aarch32
Achin Guptaa4f50c22014-05-09 12:17:56 +0100155
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100156vector_entry fiq_aarch32
Julius Werner67ebde72017-07-27 14:59:34 -0700157 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100158end_vector_entry fiq_aarch32
Achin Guptaa4f50c22014-05-09 12:17:56 +0100159
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100160vector_entry serror_aarch32
Julius Werner67ebde72017-07-27 14:59:34 -0700161 b plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100162end_vector_entry serror_aarch32