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git01.mediatek.com / filogic / atf / 8abbb9246bebbef10db0a9445b9ad0dd484092dd / . / plat / arm / board / tc / fdts / tc_spmc_optee_sp_manifest.dts
blob: 382f0e1b5f8948e644c0ee9a9cab1708ad8d92fb [file] [log] [blame]
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]1/*
J-Alves8abbb922023-05-10 11:28:38 +0100[diff] [blame^]2 * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6/dts-v1/;
7
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]8/ {
9 compatible = "arm,ffa-core-manifest-1.0";
10 #address-cells = <2>;
J-Alves8abbb922023-05-10 11:28:38 +0100[diff] [blame^]11 #size-cells = <2>;
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]12
13 attribute {
14 spmc_id = <0x8000>;
15 maj_ver = <0x1>;
J-Alves481c52f2021-03-11 17:46:47 +0000[diff] [blame]16 min_ver = <0x1>;
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]17 exec_state = <0x0>;
18 load_address = <0x0 0xfd000000>;
19 entrypoint = <0x0 0xfd000000>;
20 binary_size = <0x80000>;
21 };
22
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]23 hypervisor {
24 compatible = "hafnium,hafnium";
25 vm1 {
26 is_ffa_partition;
27 debug_name = "op-tee";
28 load_address = <0xfd280000>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]29 vcpu_count = <8>;
Davidson K9a949142021-03-10 12:07:15 +0530[diff] [blame]30#ifdef TS_SP_FW_CONFIG
31 mem_size = <26738688>; /* 25MB TZC DRAM */
32#else
33 mem_size = <30928896>; /* 29MB TZC DRAM */
34#endif
35 };
36#ifdef TS_SP_FW_CONFIG
37 vm2 {
38 is_ffa_partition;
Davidson Kea84e432021-08-10 19:25:57 +0530[diff] [blame]39 debug_name = "internal-trusted-storage";
Davidson K9a949142021-03-10 12:07:15 +0530[diff] [blame]40 load_address = <0xfee00000>;
41 vcpu_count = <1>;
42 mem_size = <2097152>; /* 2MB TZC DRAM */
43 };
44 vm3 {
45 is_ffa_partition;
46 debug_name = "crypto";
47 load_address = <0xfec00000>;
48 vcpu_count = <1>;
49 mem_size = <2097152>; /* 2MB TZC DRAM */
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]50 };
Davidson K9a949142021-03-10 12:07:15 +0530[diff] [blame]51#endif
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]52 };
53
54 cpus {
55 #address-cells = <0x2>;
56 #size-cells = <0x0>;
57
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]58 CPU0:cpu@0 {
59 device_type = "cpu";
60 compatible = "arm,armv8";
61 reg = <0x0 0x0>;
62 enable-method = "psci";
63 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]64
65 /*
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]66 * SPMC (Hafnium) requires secondary cpu nodes are declared in
67 * descending order
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]68 */
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]69 CPU7:cpu@700 {
70 device_type = "cpu";
71 compatible = "arm,armv8";
72 reg = <0x0 0x700>;
73 enable-method = "psci";
74 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]75
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]76 CPU6:cpu@600 {
77 device_type = "cpu";
78 compatible = "arm,armv8";
79 reg = <0x0 0x600>;
80 enable-method = "psci";
81 };
82
83 CPU5:cpu@500 {
84 device_type = "cpu";
85 compatible = "arm,armv8";
86 reg = <0x0 0x500>;
87 enable-method = "psci";
88 };
89
90 CPU4:cpu@400 {
91 device_type = "cpu";
92 compatible = "arm,armv8";
93 reg = <0x0 0x400>;
94 enable-method = "psci";
95 };
96
97 CPU3:cpu@300 {
98 device_type = "cpu";
99 compatible = "arm,armv8";
100 reg = <0x0 0x300>;
101 enable-method = "psci";
102 };
103
104 CPU2:cpu@200 {
105 device_type = "cpu";
106 compatible = "arm,armv8";
107 reg = <0x0 0x200>;
108 enable-method = "psci";
109 };
110
111 CPU1:cpu@100 {
112 device_type = "cpu";
113 compatible = "arm,armv8";
114 reg = <0x0 0x100>;
115 enable-method = "psci";
116 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]117 };
118
J-Alves8abbb922023-05-10 11:28:38 +0100[diff] [blame^]119 memory@0 {
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]120 device_type = "memory";
J-Alves8abbb922023-05-10 11:28:38 +0100[diff] [blame^]121 reg = <0x0 0xfd000000 0x0 0x2000000>;
122 };
123
124 memory@1 {
125 device_type = "ns-memory";
126 reg = <0x0 0x80000000 0x0 0x79000000>,
127 <0x80 0x80000000 0x1 0x80000000>;
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]128 };
129};