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git01.mediatek.com / filogic / atf / f68a084b460dc5afb360d4574b39246baa7d28d2 / . / plat / arm / board / tc0 / fdts / tc0_spmc_optee_sp_manifest.dts
blob: 221039c431de6f9bf7b6c193c3aca0785aea0a88 [file] [log] [blame]
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]1/*
2 * Copyright (c) 2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6/dts-v1/;
7
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]8/ {
9 compatible = "arm,ffa-core-manifest-1.0";
10 #address-cells = <2>;
11 #size-cells = <1>;
12
13 attribute {
14 spmc_id = <0x8000>;
15 maj_ver = <0x1>;
16 min_ver = <0x0>;
17 exec_state = <0x0>;
18 load_address = <0x0 0xfd000000>;
19 entrypoint = <0x0 0xfd000000>;
20 binary_size = <0x80000>;
21 };
22
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]23 hypervisor {
24 compatible = "hafnium,hafnium";
25 vm1 {
26 is_ffa_partition;
27 debug_name = "op-tee";
28 load_address = <0xfd280000>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame^]29 vcpu_count = <8>;
30 mem_size = <30928896>; /* 32MB TZC DRAM - SPMC region */
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]31 };
32 };
33
34 cpus {
35 #address-cells = <0x2>;
36 #size-cells = <0x0>;
37
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame^]38 CPU0:cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,armv8";
41 reg = <0x0 0x0>;
42 enable-method = "psci";
43 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]44
45 /*
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame^]46 * SPMC (Hafnium) requires secondary cpu nodes are declared in
47 * descending order
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]48 */
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame^]49 CPU7:cpu@700 {
50 device_type = "cpu";
51 compatible = "arm,armv8";
52 reg = <0x0 0x700>;
53 enable-method = "psci";
54 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]55
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame^]56 CPU6:cpu@600 {
57 device_type = "cpu";
58 compatible = "arm,armv8";
59 reg = <0x0 0x600>;
60 enable-method = "psci";
61 };
62
63 CPU5:cpu@500 {
64 device_type = "cpu";
65 compatible = "arm,armv8";
66 reg = <0x0 0x500>;
67 enable-method = "psci";
68 };
69
70 CPU4:cpu@400 {
71 device_type = "cpu";
72 compatible = "arm,armv8";
73 reg = <0x0 0x400>;
74 enable-method = "psci";
75 };
76
77 CPU3:cpu@300 {
78 device_type = "cpu";
79 compatible = "arm,armv8";
80 reg = <0x0 0x300>;
81 enable-method = "psci";
82 };
83
84 CPU2:cpu@200 {
85 device_type = "cpu";
86 compatible = "arm,armv8";
87 reg = <0x0 0x200>;
88 enable-method = "psci";
89 };
90
91 CPU1:cpu@100 {
92 device_type = "cpu";
93 compatible = "arm,armv8";
94 reg = <0x0 0x100>;
95 enable-method = "psci";
96 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000[diff] [blame]97 };
98
99 /* 32MB of TC0_TZC_DRAM1_BASE */
100 memory@fd000000 {
101 device_type = "memory";
102 reg = <0x0 0xfd000000 0x2000000>;
103 };
104};