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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PLAT_DEF_H__
32#define __PLAT_DEF_H__
33
34#define RK3399_PRIMARY_CPU 0x0
35
36/* Special value used to verify platform parameters from BL2 to BL3-1 */
37#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
38
39#define SIZE_K(n) ((n) * 1024)
40#define SIZE_M(n) ((n) * 1024 * 1024)
41
Caesar Wangad39cfe2016-07-21 10:36:22 +080042/* Register base address and size */
43#define MMIO_BASE 0xfe000000
Tony Xief6118cc2016-01-15 17:17:32 +080044
Caesar Wangad39cfe2016-07-21 10:36:22 +080045#define GIC500_BASE (MMIO_BASE + 0xe00000)
Tony Xief6118cc2016-01-15 17:17:32 +080046#define GIC500_SIZE SIZE_M(2)
47
Caesar Wangad39cfe2016-07-21 10:36:22 +080048#define PMU_BASE (MMIO_BASE + 0x1310000)
49#define PMU_SIZE SIZE_K(64)
Tony Xief6118cc2016-01-15 17:17:32 +080050
Caesar Wangad39cfe2016-07-21 10:36:22 +080051#define PMUGRF_BASE (MMIO_BASE + 0x1320000)
52#define PMUGRF_SIZE SIZE_K(64)
Tony Xief6118cc2016-01-15 17:17:32 +080053
Caesar Wangad39cfe2016-07-21 10:36:22 +080054#define SGRF_BASE (MMIO_BASE + 0x1330000)
55#define SGRF_SIZE SIZE_K(64)
Tony Xief6118cc2016-01-15 17:17:32 +080056
Caesar Wangad39cfe2016-07-21 10:36:22 +080057#define PMUSRAM_BASE (MMIO_BASE + 0x13b0000)
Tony Xief6118cc2016-01-15 17:17:32 +080058#define PMUSRAM_SIZE SIZE_K(64)
59#define PMUSRAM_RSIZE SIZE_K(8)
60
Caesar Wangad39cfe2016-07-21 10:36:22 +080061#define PWM_BASE (MMIO_BASE + 0x1420000)
62#define PWM_SIZE SIZE_K(64)
Caesar Wang59e41b52016-04-10 14:11:07 +080063
Caesar Wangad39cfe2016-07-21 10:36:22 +080064#define GPIO0_BASE (MMIO_BASE + 0x1720000)
Caesar Wang038f6aa2016-05-25 19:21:43 +080065#define GPIO0_SIZE SIZE_K(64)
66
Caesar Wangad39cfe2016-07-21 10:36:22 +080067#define GPIO1_BASE (MMIO_BASE + 0x1730000)
Caesar Wang038f6aa2016-05-25 19:21:43 +080068#define GPIO1_SIZE SIZE_K(64)
69
Caesar Wangad39cfe2016-07-21 10:36:22 +080070#define CRUS_BASE (MMIO_BASE + 0x1750000)
71#define CRUS_SIZE SIZE_K(128)
72
73#define GRF_BASE (MMIO_BASE + 0x1770000)
74#define GRF_SIZE SIZE_K(64)
75
76#define GPIO2_BASE (MMIO_BASE + 0x1780000)
Caesar Wang038f6aa2016-05-25 19:21:43 +080077#define GPIO2_SIZE SIZE_K(32)
78
Caesar Wangad39cfe2016-07-21 10:36:22 +080079#define GPIO3_BASE (MMIO_BASE + 0x1788000)
Caesar Wang038f6aa2016-05-25 19:21:43 +080080#define GPIO3_SIZE SIZE_K(32)
81
Caesar Wangad39cfe2016-07-21 10:36:22 +080082#define GPIO4_BASE (MMIO_BASE + 0x1790000)
Caesar Wang038f6aa2016-05-25 19:21:43 +080083#define GPIO4_SIZE SIZE_K(32)
84
Caesar Wangad39cfe2016-07-21 10:36:22 +080085#define STIME_BASE (MMIO_BASE + 0x1860000)
86#define STIME_SIZE SIZE_K(64)
Caesar Wang038f6aa2016-05-25 19:21:43 +080087
Caesar Wangad39cfe2016-07-21 10:36:22 +080088#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000)
Tony Xie42e113e2016-07-16 11:16:51 +080089#define NOC_0_SIZE SIZE_K(192)
90
Caesar Wangad39cfe2016-07-21 10:36:22 +080091#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000)
Tony Xie42e113e2016-07-16 11:16:51 +080092#define NOC_1_SIZE SIZE_K(16)
93
Caesar Wangad39cfe2016-07-21 10:36:22 +080094#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000)
Tony Xie42e113e2016-07-16 11:16:51 +080095#define NOC_2_SIZE SIZE_K(16)
96
Caesar Wangad39cfe2016-07-21 10:36:22 +080097#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x1a90000)
Tony Xie42e113e2016-07-16 11:16:51 +080098#define NOC_3_SIZE SIZE_K(448)
99
Caesar Wangad39cfe2016-07-21 10:36:22 +0800100#define CCI500_BASE (MMIO_BASE + 0x1b00000)
101#define CCI500_SIZE SIZE_M(1)
102
103/* Aggregate of all devices in the first GB */
104#define RK3399_DEV_RNG0_BASE MMIO_BASE
105#define RK3399_DEV_RNG0_SIZE 0x1d00000
106
Tony Xief6118cc2016-01-15 17:17:32 +0800107/*
108 * include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr
109 * 0xff650000 -0xff6c0000
110 */
Caesar Wangad39cfe2016-07-21 10:36:22 +0800111#define PD_BUS0_BASE (MMIO_BASE + 0x1650000)
112#define PD_BUS0_SIZE SIZE_K(448)
Tony Xief6118cc2016-01-15 17:17:32 +0800113
Caesar Wangad39cfe2016-07-21 10:36:22 +0800114#define PMUCRU_BASE (MMIO_BASE + 0x1750000)
115#define CRU_BASE (MMIO_BASE + 0x1760000)
Tony Xief6118cc2016-01-15 17:17:32 +0800116
Caesar Wangad39cfe2016-07-21 10:36:22 +0800117#define COLD_BOOT_BASE (MMIO_BASE + 0x1ff0000)
Tony Xief6118cc2016-01-15 17:17:32 +0800118
119/**************************************************************************
120 * UART related constants
121 **************************************************************************/
122#define RK3399_UART2_BASE (0xff1a0000)
123#define RK3399_UART2_SIZE SIZE_K(64)
124
Caesar Wang5a7131e2016-04-19 20:42:17 +0800125#define RK3399_BAUDRATE (115200)
Tony Xief6118cc2016-01-15 17:17:32 +0800126#define RK3399_UART_CLOCK (24000000)
127
128/******************************************************************************
129 * System counter frequency related constants
130 ******************************************************************************/
131#define SYS_COUNTER_FREQ_IN_TICKS 24000000
Tony Xief6118cc2016-01-15 17:17:32 +0800132
133/* Base rockchip_platform compatible GIC memory map */
134#define BASE_GICD_BASE (GIC500_BASE)
135#define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1))
136
137/*****************************************************************************
138 * CCI-400 related constants
139 ******************************************************************************/
140#define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 0
141#define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 1
142
143/******************************************************************************
Tony Xief6118cc2016-01-15 17:17:32 +0800144 * sgi, ppi
145 ******************************************************************************/
146#define ARM_IRQ_SEC_PHY_TIMER 29
147
148#define ARM_IRQ_SEC_SGI_0 8
149#define ARM_IRQ_SEC_SGI_1 9
150#define ARM_IRQ_SEC_SGI_2 10
151#define ARM_IRQ_SEC_SGI_3 11
152#define ARM_IRQ_SEC_SGI_4 12
153#define ARM_IRQ_SEC_SGI_5 13
154#define ARM_IRQ_SEC_SGI_6 14
155#define ARM_IRQ_SEC_SGI_7 15
156/*
157 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
158 * terminology. On a GICv2 system or mode, the lists will be merged and treated
159 * as Group 0 interrupts.
160 */
161#define RK3399_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER
162#define RK3399_G0_IRQS ARM_IRQ_SEC_SGI_6
163
Caesar Wangad39cfe2016-07-21 10:36:22 +0800164#define PWM0_IOMUX_PWM_EN (1 << 0)
165#define PWM1_IOMUX_PWM_EN (1 << 1)
166#define PWM2_IOMUX_PWM_EN (1 << 2)
167#define PWM3_IOMUX_PWM_EN (1 << 3)
168
169#define PWM_CNT(n) 0x0000 + 0x10 * n
170#define PWM_PERIOD_HPR(n) 0x0004 + 0x10 * n
171#define PWM_DUTY_LPR(n) 0x0008 + 0x10 * n
172#define PWM_CTRL(n) 0x000c + 0x10 * n
173
Tony Xief6118cc2016-01-15 17:17:32 +0800174#endif /* __PLAT_DEF_H__ */