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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
7#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <drivers/arm/gicv2.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -08009#include <platform_def.h>
10
11 .globl plat_secondary_cold_boot_setup
12 .globl plat_is_my_cpu_primary
Antonio Nino Diazea3c4de2018-10-17 16:46:41 +010013 .globl zynqmp_calc_core_pos
14 .globl plat_my_core_pos
Antonio Nino Diazea3c4de2018-10-17 16:46:41 +010015 .globl platform_mem_init
Soren Brinkmann76fcae32016-03-06 20:16:27 -080016
17 /* -----------------------------------------------------
18 * void plat_secondary_cold_boot_setup (void);
19 *
20 * This function performs any platform specific actions
21 * needed for a secondary cpu after a cold reset e.g
22 * mark the cpu's presence, mechanism to place it in a
23 * holding pen etc.
24 * TODO: Should we read the PSYS register to make sure
25 * that the request has gone through.
26 * -----------------------------------------------------
27 */
28func plat_secondary_cold_boot_setup
29 mrs x0, mpidr_el1
30
31 /* Deactivate the gic cpu interface */
32 ldr x1, =BASE_GICC_BASE
33 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
34 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
35 str w0, [x1, #GICC_CTLR]
36
37 /*
38 * There is no sane reason to come out of this wfi. This
39 * cpu will be powered on and reset by the cpu_on pm api
40 */
41 dsb sy
421:
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000043 no_ret plat_panic_handler
Soren Brinkmann76fcae32016-03-06 20:16:27 -080044endfunc plat_secondary_cold_boot_setup
45
46func plat_is_my_cpu_primary
47 mov x9, x30
48 bl plat_my_core_pos
49 cmp x0, #ZYNQMP_PRIMARY_CPU
50 cset x0, eq
51 ret x9
52endfunc plat_is_my_cpu_primary
Antonio Nino Diazea3c4de2018-10-17 16:46:41 +010053
54 /* -----------------------------------------------------
55 * unsigned int plat_my_core_pos(void)
56 * This function uses the zynqmp_calc_core_pos()
57 * definition to get the index of the calling CPU.
58 * -----------------------------------------------------
59 */
60func plat_my_core_pos
61 mrs x0, mpidr_el1
62 b zynqmp_calc_core_pos
63endfunc plat_my_core_pos
64
65 /* -----------------------------------------------------
66 * unsigned int zynqmp_calc_core_pos(u_register_t mpidr)
67 * Helper function to calculate the core position.
68 * With this function: CorePos = (ClusterId * 4) +
69 * CoreId
70 * -----------------------------------------------------
71 */
72func zynqmp_calc_core_pos
73 and x1, x0, #MPIDR_CPU_MASK
74 and x0, x0, #MPIDR_CLUSTER_MASK
75 add x0, x1, x0, LSR #6
76 ret
77endfunc zynqmp_calc_core_pos
78
Antonio Nino Diazea3c4de2018-10-17 16:46:41 +010079 /* ---------------------------------------------------------------------
80 * We don't need to carry out any memory initialization on ARM
81 * platforms. The Secure RAM is accessible straight away.
82 * ---------------------------------------------------------------------
83 */
84func platform_mem_init
85 ret
86endfunc platform_mem_init