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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <asm_macros.S>
32#include <gicv2.h>
33#include <platform_def.h>
34
35 .globl plat_secondary_cold_boot_setup
36 .globl plat_is_my_cpu_primary
37
38 /* -----------------------------------------------------
39 * void plat_secondary_cold_boot_setup (void);
40 *
41 * This function performs any platform specific actions
42 * needed for a secondary cpu after a cold reset e.g
43 * mark the cpu's presence, mechanism to place it in a
44 * holding pen etc.
45 * TODO: Should we read the PSYS register to make sure
46 * that the request has gone through.
47 * -----------------------------------------------------
48 */
49func plat_secondary_cold_boot_setup
50 mrs x0, mpidr_el1
51
52 /* Deactivate the gic cpu interface */
53 ldr x1, =BASE_GICC_BASE
54 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
55 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
56 str w0, [x1, #GICC_CTLR]
57
58 /*
59 * There is no sane reason to come out of this wfi. This
60 * cpu will be powered on and reset by the cpu_on pm api
61 */
62 dsb sy
631:
64 bl plat_panic_handler
65endfunc plat_secondary_cold_boot_setup
66
67func plat_is_my_cpu_primary
68 mov x9, x30
69 bl plat_my_core_pos
70 cmp x0, #ZYNQMP_PRIMARY_CPU
71 cset x0, eq
72 ret x9
73endfunc plat_is_my_cpu_primary