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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
Jay Buddhabhatti6a44ad02023-02-28 01:23:04 -08003 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05304 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <common/interrupt_props.h>
9#include <drivers/arm/gicv3.h>
10#include <lib/utils.h>
11#include <plat/common/platform.h>
12
Prasad Kummari536e1102023-06-22 10:50:02 +053013#include <plat_private.h>
14#include <platform_def.h>
15
16
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053017/******************************************************************************
18 * The following functions are defined as weak to allow a platform to override
19 * the way the GICv3 driver is initialised and used.
20 *****************************************************************************/
21#pragma weak plat_versal_gic_driver_init
22#pragma weak plat_versal_gic_init
23#pragma weak plat_versal_gic_cpuif_enable
24#pragma weak plat_versal_gic_cpuif_disable
25#pragma weak plat_versal_gic_pcpu_init
26#pragma weak plat_versal_gic_redistif_on
27#pragma weak plat_versal_gic_redistif_off
28
29/* The GICv3 driver only needs to be initialized in EL3 */
30static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
31
32static const interrupt_prop_t versal_interrupt_props[] = {
33 PLAT_VERSAL_G1S_IRQ_PROPS(INTR_GROUP1S),
34 PLAT_VERSAL_G0_IRQ_PROPS(INTR_GROUP0)
35};
36
37/*
38 * We save and restore the GICv3 context on system suspend. Allocate the
39 * data in the designated EL3 Secure carve-out memory.
40 */
Chris Kay33bfc5e2023-02-14 11:30:04 +000041static gicv3_redist_ctx_t rdist_ctx __section(".versal_el3_tzc_dram");
42static gicv3_dist_ctx_t dist_ctx __section(".versal_el3_tzc_dram");
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053043
44/*
45 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
46 * to core position.
47 *
48 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
49 * values read from GICR_TYPER don't have an MT field. To reuse the same
50 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
51 * that read from GICR_TYPER.
52 *
53 * Assumptions:
54 *
55 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
56 * - No CPUs implemented in the system use affinity level 3.
57 */
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053058static uint32_t versal_gicv3_mpidr_hash(u_register_t mpidr)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053059{
60 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
61 return versal_calc_core_pos(mpidr);
62}
63
64static const gicv3_driver_data_t versal_gic_data __unused = {
Jay Buddhabhatti6da87942023-10-05 05:21:50 -070065 .gicd_base = PLAT_ARM_GICD_BASE,
66 .gicr_base = PLAT_ARM_GICR_BASE,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053067 .interrupt_props = versal_interrupt_props,
68 .interrupt_props_num = ARRAY_SIZE(versal_interrupt_props),
69 .rdistif_num = PLATFORM_CORE_COUNT,
70 .rdistif_base_addrs = rdistif_base_addrs,
71 .mpidr_to_core_pos = versal_gicv3_mpidr_hash
72};
73
74void __init plat_versal_gic_driver_init(void)
75{
76 /*
77 * The GICv3 driver is initialized in EL3 and does not need
78 * to be initialized again in SEL1. This is because the S-EL1
79 * can use GIC system registers to manage interrupts and does
80 * not need GIC interface base addresses to be configured.
81 */
82#if IMAGE_BL31
83 gicv3_driver_init(&versal_gic_data);
84#endif
85}
86
87/******************************************************************************
88 * Versal common helper to initialize the GIC. Only invoked by BL31
89 *****************************************************************************/
90void __init plat_versal_gic_init(void)
91{
92 gicv3_distif_init();
93 gicv3_rdistif_init(plat_my_core_pos());
94 gicv3_cpuif_enable(plat_my_core_pos());
95}
96
97/******************************************************************************
98 * Versal common helper to enable the GIC CPU interface
99 *****************************************************************************/
100void plat_versal_gic_cpuif_enable(void)
101{
102 gicv3_cpuif_enable(plat_my_core_pos());
103}
104
105/******************************************************************************
106 * Versal common helper to disable the GIC CPU interface
107 *****************************************************************************/
108void plat_versal_gic_cpuif_disable(void)
109{
110 gicv3_cpuif_disable(plat_my_core_pos());
111}
112
113/******************************************************************************
114 * Versal common helper to initialize the per-cpu redistributor interface in
115 * GICv3
116 *****************************************************************************/
117void plat_versal_gic_pcpu_init(void)
118{
119 gicv3_rdistif_init(plat_my_core_pos());
120}
121
122/******************************************************************************
123 * Versal common helpers to power GIC redistributor interface
124 *****************************************************************************/
125void plat_versal_gic_redistif_on(void)
126{
127 gicv3_rdistif_on(plat_my_core_pos());
128}
129
130void plat_versal_gic_redistif_off(void)
131{
132 gicv3_rdistif_off(plat_my_core_pos());
133}
134
135/******************************************************************************
136 * Versal common helper to save & restore the GICv3 on resume from system
137 * suspend
138 *****************************************************************************/
139void plat_versal_gic_save(void)
140{
141 /*
142 * If an ITS is available, save its context before
143 * the Redistributor using:
144 * gicv3_its_save_disable(gits_base, &its_ctx[i])
145 * Additionnaly, an implementation-defined sequence may
146 * be required to save the whole ITS state.
147 */
148
149 /*
150 * Save the GIC Redistributors and ITS contexts before the
151 * Distributor context. As we only handle SYSTEM SUSPEND API,
152 * we only need to save the context of the CPU that is issuing
153 * the SYSTEM SUSPEND call, i.e. the current CPU.
154 */
155 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
156
157 /* Save the GIC Distributor context */
158 gicv3_distif_save(&dist_ctx);
159
160 /*
161 * From here, all the components of the GIC can be safely powered down
162 * as long as there is an alternate way to handle wakeup interrupt
163 * sources.
164 */
165}
166
167void plat_versal_gic_resume(void)
168{
169 /* Restore the GIC Distributor context */
170 gicv3_distif_init_restore(&dist_ctx);
171
172 /*
173 * Restore the GIC Redistributor and ITS contexts after the
174 * Distributor context. As we only handle SYSTEM SUSPEND API,
175 * we only need to restore the context of the CPU that issued
176 * the SYSTEM SUSPEND call.
177 */
178 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
179
180 /*
181 * If an ITS is available, restore its context after
182 * the Redistributor using:
183 * gicv3_its_restore(gits_base, &its_ctx[i])
184 * An implementation-defined sequence may be required to
185 * restore the whole ITS state. The ITS must also be
186 * re-enabled after this sequence has been executed.
187 */
188}