refactor(xilinx): rename gic macros to make common
Rename macros PLAT_VERSAL_GICD_BASE, PLAT_VERSAL_GICR_BASE,
PLAT_VERSAL_NET_GICD_BASE and PLAT_VERSAL_NET_GICR_BASE to
PLAT_GICD_BASE_VALUE and PLAT_GICR_BASE_VALUE to make common
for both Versal and Versal NET platforms.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ibcebfb8e741e828ef272b32cbedfb4dcbf8629b6
diff --git a/plat/xilinx/versal/versal_gicv3.c b/plat/xilinx/versal/versal_gicv3.c
index 0959c8e..4f4e0d9 100644
--- a/plat/xilinx/versal/versal_gicv3.c
+++ b/plat/xilinx/versal/versal_gicv3.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -60,8 +61,8 @@
}
static const gicv3_driver_data_t versal_gic_data __unused = {
- .gicd_base = PLAT_VERSAL_GICD_BASE,
- .gicr_base = PLAT_VERSAL_GICR_BASE,
+ .gicd_base = PLAT_GICD_BASE_VALUE,
+ .gicr_base = PLAT_GICR_BASE_VALUE,
.interrupt_props = versal_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(versal_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,